Mathematical reasoning aims to infer satisfiable solutions based on the given mathematics questions.Previous natural language processing researches have proven the effectiveness of sequence-to-sequence (Seq2Seq) or related variants on mathematics solving.However, few works have been able to explore structural or syntactic information hidden in expressions (e.g., precedence and associativity).This dissertation set out to investigate the usefulness of such untapped information for neural architectures.Firstly, mathematical questions are represented in the format of graphs within syntax analysis.The structured nature of graphs allows them to represent relations of variables or operators while preserving the semantics of the expressions.Having transformed to the new representations, we proposed a graph-to-sequence neural network GraphMR, which can effectively learn the hierarchical information of graphs inputs to solve mathematics and speculate answers.A complete experimental scenario with four classes of mathematical tasks and three Seq2Seq baselines is built to conduct a comprehensive analysis, and results show that GraphMR outperforms others in hidden information learning and mathematics resolving.

Satisfiability Modulo Theories (SMT) solvers have been widely applied in automated software analysis to reason about the queries that encode the essence of program semantics, relieving the heavy burden of manual analysis. Many SMT solving techniques rely on solving Boolean satisfiability problem (SAT), which is an NP-complete problem, so they use heuristic search strategies to seek possible solutions, especially when no known theorem can efficiently reduce the problem. An emerging challenge, named Mixed-Bitwise-Arithmetic (MBA) obfuscation, impedes SMT solving by constructing identity equations with both bitwise operations (and, or, negate) and arithmetic computation (add, minus, multiply). Common math theorems for bitwise or arithmetic computation are inapplicable to simplifying MBA equations, leading to performance bottlenecks in SMT solving.

With the increasing popularity of shared-memory programming model, especially at the advent of multicore processors, applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Traditionally locks are used to enforce data dependence and timing constraints between the various threads. However locks are error- prone, and often leading to unwanted race conditions, priority inversion, or deadlock. Therefore, recent waves of research projects are exploring transaction memory systems as an alternative synchronization mechanism to locks. This paper presents a software transactional memory execution model for parallel multithread programming without lock.

Multi-core processors can easily provide benefits for multithreaded workloads, but many applications written for uniprocessors cannot automatically benefit from chip multiprocessors (CMP) designs. This paper presents a reverse compilation framework, which translates existing binary code without source code to the static single assignment (SSA) form, and then the internal SSA form is applied by the compilation phase to generate the speculative parallel threading (SPT) code. A profiler is applied to optimize the code dynamically during execution. The evaluation results show that these existing binary codes without source codes execute on CMP with performance improved, due to taking advantage of the speculative parallel threading support provided by the processor