We introduce machine learning-based solutions for differentiating wafers fabricated using trusted and untrusted mask-sets based on the typical metrology or wafer acceptance tests collected during semiconductor manufacturing and testing. Our methods leverage the systematic nature of process variation and capture the subtle causality between mask modifications and either physical dimensions or electrical characteristics of the produced silicon, which can then be used for the purpose of wafer-level mask-set attestation. Effectiveness of our solutions is demonstrated on a dataset of inline and e-test measurements from 8000 wafers fabricated with multiple variants of a mask-set in the GlobalFoundries 12LP FinFET technology node.

We demonstrate the value of integrating expert-level domain knowledge into Machine Learning (ML) model training, which becomes particularly important when modeling complex processes such as semiconductor manufacturing. Specifically, we discuss a machine learning-based methodology which correlates physical metrology measurements with process control monitoring electrical measurements by employing Multivariate Adaptive Regression Splines (MARS) and Non-Dominating Sorting Genetic Algorithm II (NSGA-II). Baseline effectiveness of this solution in predicting critical measurements for maintaining fabrication process integrity, such as yield shorts, ring oscillator active mode current (IDDA) and frequency differences, is assessed using actual High Volume Manufacturing (HVM) production data from an advanced FinFET technology node. Further improvements, however, can be obtained by leveraging domain-specific expertise. Indeed, as we demonstrate experimentally, model accuracy, training time, and explainability all improve when such expertise is integrated in the training process. Our results highlight the pitfalls of blindly applying machine learning and illustrate the value of including semiconductor experts in the development of machine learning models for process optimization-related tasks.

We discuss the problem of generating synthetic Process Control Monitoring (PCM) data and evaluating how accurately it reflects the distribution of actual measurements from manufactured wafers. PCMs are small test structures placed in the scribe lines of the wafer, on which electrical tests (E-tests) are conducted to monitor the impact of process variation on a manufactured wafer. Besides its immediate use in assessing and controlling wafer health, collective PCM data holds invaluable information for process engineers who seek to maximize yield and performance across process corners. Yet availability of such data is limited during the ramp-up phase of a process, when it is needed the most. To address this limitation, we introduce a methodology that leverages correlations across E-test measurements and across wafer locations to generate a large synthetic population from a small data sample. Furthermore, we discuss statistical metrics that can be used to evaluate the accuracy of the synthetically generated vis-à-vis the actual population. Effectiveness of our solution is experimentally validated using E-test data from ~8K wafers fabricated in an advanced GlobalFoundries FinFET node.

This work studies a data-driven methodology for detecting systematic defects using layout-aware scan diagnosis data. As part of volume diagnosis, this methodology focuses on ranking the most systematic defective signatures, while possible random defects are also present in the wafer. The main analysis components utilize χ2Independence Tests to establish systematic relationships between reported defective signatures and defects, while data clustering and net repeating signals are used to amplify these systematic defective signals. Based on consensus results from the analysis components, the methodology provides physical candidates to facilitate the discovery of potential yield limiters. Finally, methodology effectiveness and evaluations are presented through application on production wafers from three 14nm products.

Yield estimation is an indispensable piece of information at the onset of high-volume production of a device, as it can inform timely process and design refinements in order to achieve high yield, rapid ramp-up, and fast time-to-market. To date, yield estimation is generally performed through simulation-based methods. However, such methods are not only very time-consuming for certain circuit classes, but also limited by the accuracy of the statistical models provided in the process design kits (PDKs). In contrast, herein we introduce yield estimation solutions which rely exclusively on silicon measurements and we apply them toward predicting yield during: 1) production migration from one fabrication facility to another and 2) transition from one design generation to the next. These solutions are applicable to any circuit, regardless of PDK accuracy and transistor-level simulation complexity, and range from rather straightforward to more sophisticated ones, capable of leveraging additional sources of silicon data. Effectiveness of the proposed yield forecasting methods is evaluated using actual high-volume production data from two 65-nm RF transceiver devices.

We describe a framework for characterizing systematic variations and failures through exploring the hidden patterns of test data from multiple test stages. The framework provides prediction of process variations with a fine resolution based on a limited number of probed process parameters. An unsupervised biclustering technique is then utilized to extract grayscale and binary spatial patterns from process parameters and production test results, respectively, through analyzing both item-to-item and die-to-die correlations in subsets of the test data. A template matching technique exploits these spatial patterns to discover connections between process variations and failures detected by production tests. The proposed framework has been verified by an industrial test dataset of a non-volatile memory product. The discovery of comprehensible correlations between process parameters and some production test items was confirmed by the engineers who have insights to the test dataset.

This paper describes a volume diagnosis infrastructure built on open-source software, which addresses practical challenges in a foundry environment by integrating various data sources from design, manufacturing process and test to enable rapid root-cause identification.

Outlier screening is a popular approach for testing automotive products. In practice, developing an outlier model can be subjective, making justification of the model challenging. In this paper we propose a new concept called Consistency which provides a data-driven objective way to assess an outlier model. We study the development of outlier models in view of this new model consistency concept and report experimental findings on an automotive product line.

We investigate the utility of correlations between e-test and probe test measurements in predicting yield. Specifically, we first examine whether statistical methods can accurately predict parametric probe test yield as a function of e-test measurements within the same fab. Then, we investigate whether the e-test profile of a destination fab, in conjunction with the e-test and probe test profiles of a source fab, suffice for accurate yield prognosis during fab-to-fab product migration. Results using an industrial dataset of ~3.5M devices from a 65nm Texas Instruments RF transceiver design fabricated in two different fabs reveal that (i) within-fab yield prediction error is in the range of a few tenths of a percentile point, and (ii) fab-to-fab yield prediction error is in the range of half a percentile point.

We introduce two statistical methods for identifying recycled integrated circuits (ICs) through the use of one-class classifiers and degradation curve sensitivity analysis. Both methods rely on statistically learning the parametric behavior of known new devices and using it as a reference point to determine whether a device under authentication has previously been used. The proposed methods are evaluated using actual measurements and simulation data from digital and analog devices, with experimental results confirming their effectiveness in distinguishing between new and aged ICs and their superiority over previously proposed methods.

Wafer-level spatial correlation modeling of probetest measurements has been explored in the past as an avenue to test cost and test time reduction. In this work, we first improve the accuracy of a popular Gaussian process-based wafer-level spatial correlation method through two key enhancements: (i) confidence estimation-based progressive sampling, and, (ii) inclusion of spatio-temporal features for inter-wafer trend learning. We then explore a new application of the enhanced correlation modeling method in estimating High Volume Manufacturing (HVM) yield from a small set of early wafers and we demonstrate its effectiveness on a large set of actual industrial test data.

Laser trimming is used extensively to ensure accurate values of on-chip precision resistors in the presence of process variations. Such laser resistor trimming is slow and expensive, typically performed in a closed-loop, where the laser is iteratively fired and some circuit parameter (i.e. current) is monitored until a target condition is satisfied. Toward reducing this cost, we introduce a novel methodology for predicting the laser trim length, thereby eliminating the closed-loop control and speeding up the process. Predictions are obtained from waferlevel spatial correlation models, learned from a sparse sample of die on which traditional trimming is performed. Effectiveness is demonstrated on an actual wafer of laser-trimmed ICs.

In this paper, a novel Bayesian model fusion (BMF) method is proposed for test cost reduction based on wafer-level spatial variation modeling. BMF relies on the assumption that a large number of wafers of the same circuit design (e.g., all wafers from the same lot) share a similar spatial pattern. Hence, the measurement data from one wafer can be borrowed to model the spatial variation of other wafers via Bayesian inference. By applying the Sherman-Morrison-Woodbury formula, a fast numerical algorithm is derived to reduce the computational cost of BMF for practical test applications. Furthermore, a new test methodology is developed based on BMF and it closely monitors the escape rate and yield loss. As is demonstrated by the wafer probe measurement data of an industrial RF transceiver, BMF achieves 1.125× reduction in test cost and 2.6× reduction in yield loss, compared to the conventional approach based on virtual probe (VP).

Finding the cause of yield and reliability issues has never been an easy task for the product and test engineer. The challenge continues to grow as processes add more steps and contain more complicated interactions, as designs are pushed to the limits of the process capabilities to meet their market requirements, as DPPM requirements continue to lower, and as test costs do not scale well. Test data has continued to become more critical in quickly resolving issues for fast ramps and maintenance of quality levels. However, the analysis methods are becoming more sophisticated and data intensive. This presentation will review some case studies, what was learned, and some observations.

A lot has changed in two years. This presentation will review what is new for the Y2013 ITRS major revision. This revision focuses more on explaining adaptive test beyond the expert users. What are emerging opportunities/challenges? What are the biggest upcoming bottlenecks?

Performance degradation due to transistor aging is a significant impediment to high-performance IC design due to increasing concerns of reliability mechanisms such as negative-bias-temperature-instability (NBTI). The concern only grows with technology scaling as the effects of positive bias temperature instability (PBTI) is becoming prominent in future technologies and compounding with the effects of NBTI. Although aging of transistor is inevitable and the magnitude of degradation due to aging varies depending upon the context. Specifically, in power-efficient systems designs, the logic and clock paths are susceptible to static stress resulting in peak degradation due to BTI occurrence when clock is gated. In this article, we present the reliability impact of making systems power efficient and propose a design-for-reliability methodology that can be used in conjunction with low-power design techniques to alleviate the stress conditions caused by rendering circuits in idle state. The technique— BTI-Refresh , is shown to be applicable to both logic and clock paths alike and focuses on preventing prolonged static stress using periodic refreshes to achieve alternating stress. The mechanism is shown to integrate seamlessly into the design at gate-level without requiring any architectural or RT-level changes. Using ISCAS benchmarks and Kogge-Stone-Adder circuits, it is shown to reduce the aging effect in logic path delay due to static stress by up to 50% with negligible area and power overhead. BTI-Refresh is extended to clock-paths to prevent pulse-width degradation due to static aging and with minimal clock-skew.

As the electronic component supply chain grows more complex due to globalization, with parts coming from a diverse set of suppliers, counterfeit electronics have become a major challenge that calls for immediate solutions. Currently, there are a few standards and programs available that address the testing for such counterfeit parts. However, not enough research has yet addressed the detection and avoidance of all counterfeit parts-recycled, remarked, overproduced, cloned, out-of-spec/defective, and forged documentation-currently infiltrating the electronic component supply chain. Even if they work initially, all these parts may have reduced lifetime and pose reliability risks. In this tutorial, we will provide a review of some of the existing counterfeit detection and avoidance methods. We will also discuss the challenges ahead for implementing these methods, as well as the development of new detection and avoidance mechanisms.

In an effort to reduce the cost of specification testing in analog/RF circuits, spatial correlation modeling of wafer-level measurements has recently attracted increased attention. Existing approaches for capturing and leveraging such correlation, however, rely on the assumption that spatial variation is smooth and continuous. This, in turn, limits the effectiveness of these methods on actual production data, which often exhibits localized spatial discontinuous effects. In this work, we propose a novel approach which enables spatial correlation modeling of wafer-level analog/RF tests to handle such effects and, thereby, to drastically reduce prediction error for measurements exhibiting discontinuous spatial patterns. The core of the proposed approach is a k-means algorithm which partitions a wafer into k clusters, as caused by discontinuous effects. Individual correlation models are then constructed within each cluster, revoking the assumption that spatial patterns should be smooth and continuous across the entire wafer. Effectiveness of the proposed approach is evaluated on industrial probe test data from more than 3,400 wafers, revealing significant error reduction over existing approaches.

Statistical intra-die correlation has been extensively studied as a means for reducing test cost in analog/RF ICs. Generally known as alternate test, this approach seeks to predict the performances of an analog/RF chip based on low-cost measurements on the same chip and statistical models learned from a training set of chips. Recently, an orthogonal direction for leveraging statistical correlation towards reducing test cost of analog/RF ICs has also gained traction. Specifically, inter-die spatial correlation models learned from specification tests on a sparse subset of die on a wafer are used to predict performances on the unobserved die. In this work, we investigate the potential of combining these two statistical approaches, anticipating that the performance prediction accuracy of the joint correlation model will surpass the accuracy of its constituents. Experimental results on industrial semiconductor manufacturing data validate this conjecture and corroborate the utility of the combined performance prediction models.

A realistic, as opposed to fixed pessimistic end-of-life method to identify paths that are at-risk to excessive degradation due to aging is presented. It uses library cell grading information to assess the cells/instances for their sensitivity to parametric degradation.

The discovery of patterns and correlations hidden in the test data could help reduce test time and cost. In this paper, we propose a methodology and supporting statistical regression tools that can exploit and utilize both spatial and inter-test-item correlations in the test data for test time and cost reduction. We first describe a statistical regression method, called group lasso, which can identify inter-test-item correlations from test data. After learning such correlations, some test items can be identified for removal from the test program without compromising test quality. An extended version of this method, weighted group lasso, allows taking into account the distinct test time/cost of each individual test item in the formulation as a weighted optimization problem. As a result, its solution would favor more costly test items for removal from the test program. We further integrate weighted group lasso with another statistical regression technique, virtual probe, which can learn spatial correlations of test data across a wafer. The integrated method could then utilize both spatial and inter-test-item correlations to maximize the number of test items whose values can be predicted without measurement. Experimental results of a high-volume industrial device show that utilizing both spatial and inter-test-item correlations can help reduce test time by up to 55%.

As the supply chain of electronic circuits grows more complex, with parts coming from different suppliers scattered across the globe, counterfeit integrated circuits (ICs) are becoming a serious challenge which calls for immediate solutions. Counterfeiting includes re-labeling legitimate chips or illegitimately replicating chips and deceptively selling them as made by the legitimate manufacturer, or simply selling fake chips. Counterfeiting also includes providing defective parts or simply previously used parts recycled from scrapped assemblies. Obviously, there is a multitude of legal and financial implications involved in such activities and even if these devices initially work, they may have reduced lifetime and may pose reliability risks. In this tutorial, we provide a comprehensive review of existing techniques which seek to prevent and/or detect counterfeit integrated circuits. Various approaches are discussed and an advanced machine learning-based method employing parametric measurements is described in detail.

Monitoring the semiconductor manufacturing process and understanding the various sources of variation and their repercussions is a crucial capability. Indeed, identifying the root-cause of device failures, enhancing yield of future production through improvement of the manufacturing environment, and providing feedback to the designer toward development of design techniques that minimize failure rate rely on such a capability. To this end, we introduce a spatial decomposition method for breaking down the variation of a wafer to its spatial constituents, based on a small number of measurements sampled across the wafer. We demonstrate that by leveraging domain-specific knowledge and by using as constituents dynamically learned, interpretable basis functions, the ability of the proposed method to accurately identify the sources of variation is drastically improved, as compared to existing approaches. We then illustrate the utility of the proposed spatial variation decomposition method in (i) identifying the main contributor to yield variation, (ii) predicting the actual yield of a wafer, and (iii) clustering wafers for production planning and abnormal wafer identification purposes. Results are reported on industrial data from high-volume manufacturing, confirming the ability of the proposed method to provide great insight regarding the sources of variation in the semiconductor manufacturing process.

Test cost reduction for RF devices has been an ongoing topic of interest to the semiconductor manufacturing industry. Automated test equipment designed to collect parametric measurements, particularly at high frequencies, can be very costly. Together with lengthy set up and test times for certain measurements, these cause amortized test cost to comprise a high percentage of the total cost of manufacturing semiconductor devices. In this work, we investigate a spatial correlation modeling approach using Gaussian process models to enable extrapolation of performances via sparse sampling of probe test data. The proposed method performs an order of magnitude better than existing spatial sampling methods, while requiring an order of magnitude less time to construct the prediction models. The proposed methodology is validated on manufacturing data using 57 probe test measurements across more than 3,000 wafers. By explicitly applying probe tests to only 1% of the die on each wafer, we are able to predict probe test outcomes for the remaining die within 2% of their true values.

In the course of semiconductor manufacturing, various e-test measurements (also known as inline or kerf measurements) are collected to monitor the health-of-line and to make wafer scrap decisions preceding final test. These measurements are typically sampled spatially across the surface of the wafer from between-die scribe line sites, and include a variety of measurements that characterize the wafer's position in the process distribution. However, these measurements are often only used for wafer-level characterization by process and test teams, as the sampling can be quite sparse across the surface of the wafer. In this work, we introduce a novel methodology for extrapolating sparsely sampled e-test measurements to every die location on a wafer using Gaussian process models. Moreover, we introduce radial variation modeling to address variation along the wafer center-to-edge radius. The proposed methodology permits process and test engineers to examine e-test measurement outcomes at the die level, and makes no assumptions about wafer-to-wafer similarity or stationarity of process statistics over time. Using high volume manufacturing (HVM) data from industry, we demonstrate highly accurate cross-wafer spatial predictions of e-test measurements on more than 8,000 wafers.

This paper introduces an adaptive test method to dynamically control test flow and test contents with continuous per die updates of test fail rates. The method employs Bayesian statistics to model a separate fail rate for each test. Test reordering and elimination is based on statistics of these predicted fail rates and is naturally monitored by a wafer based reset. Wafer sort test response data for two 65nm integrated circuit products is used to demonstrate this method. Test time reductions of about 30% are achieved with quality levels within industry expectations.

Adaptive testing is a generic term for a number of techniques which aim at improving the test quality and/or reducing the test application costs. In adaptive tests, the test content or pass/fail limits are not fixed as in conventional tests, but dependent on other test results of the currently or previously tested chips. Part-average testing, outlier detection, and neighborhood screening are just a few examples of adaptive testing. With this Embedded Tutorial, we are offering an introduction to this topic, which is hot in the test community, to the wider DATE audience.

Quality improvement and cost reduction in the overall IC manufacturing and test processes are being continuously sought. Outlier screening methods can address both of these needs. As technology scales, it has become increasingly difficult to screen outliers without excessive Type I or II errors. Hundreds of parameters are collected at wafer probe, but there lacks a systematic way of selecting outlier screens. In this paper we describe a statistical approach to both identify outliers and select beneficial screening parameters more effectively. Results on a 90 nm design to reduce the burn-in fails are described.

The Williams and Brown model has long been the gold standard for estimating test escape rate as a function of yield and fault coverage. However, today's test programs have a number of differing test types, often with overlapping failing unit detections. This paper details the development of a method which permits test escape rate predictions based on product yield and multiple overlapping test coverages.

The ability to meet ever more demanding customer quality and reliability requirements is becoming increasingly difficult with each advancing technology generation. This issue becomes more complex as customer applications and requirements become more varied for the same basic technology. The customer applications range from cell phones and PDAs to servers to automotive. The reliability requirement descriptions vary from hundreds of defective parts per million (DPPM) to five nines availability to a zero defects culture. This paper focus on how customer quality and reliability expectations are influencing the perception and direction of test

A systematic test methodology is presented that comprehends the impact of negative bias temperature instability on product parametric drift. In specific NBTI degradation mechanisms in digital CMOS circuits and transistors are presented. A test guard-banding technique to estimate parameter drift under BI and customer use conditions is also given.