Our research introduces a novel method to identifying floating garbage debris using deep learning and High Performance Edge Computing (HPEC). We utilize a convolutional neural network (CNN) to classify debris from images captured by an RGB camera on a vessel, aiming for high accuracy and efficiency on low-power devices. We conducted a comparative analysis of various models, implementing optimization techniques like transfer learning and pruning. Each model was evaluated for accuracy, inference time, and energy consumption, leading us to develop a multi-objective function to determine the best approach. Our findings show that the proposed method effectively detects and classifies floating debris on desktop GPUs and low-power devices such as the Jetson Nano. Furthermore, it maintains accuracy by optimizing memory and computational power requirements while adapting to different energy needs. These advancements can enhance the capacity to combat marine plastic pollution and promote intelligent systems integration within environmental initiatives. They facilitate precise, real-time detection of floating debris on energy-constrained edge platforms, thereby effectively addressing deployment challenges in marine environments.

This work assesses the reliability of a hyperspectral image classifier for edge devices under transient faults by using a fine-grain strategy based on the Hardware Injection Through Program Transformation (HITPT) technique. The results identified the most vulnerable software parts and the corruption effects due to hardware faults (from 5.1% to 100.0% of accuracy drop). Then, the results supported the adoption of a selective-hardening software mechanism (based on the Duplication with Comparison strategy) to effectively mitigate the most critical effects under limited costs.

Modern HPC systems must be designed considering different parameters, which include cost, performance, and throughput, as well as non-functional properties, such as power/energy consumption and reliability. This paper describes the work performed and the results achieved by the partners of the Italian National Research Center for HPC, Big Data and Quantum Computing in the frame of the sub-project dealing with Future HPC architectures and solutions. The work in this subproject focused on advanced design and monitoring techniques for devising energy- and power-efficient, reliable parallel architectures based on open standards (e.g., RISC-V) and design space exploration techniques and tools. This paper provides a summary of the achieved results and developed products stemming from the activities of the different partners.

In the Noisy Intermediate-Scale Quantum (NISQ) era, efficient quantum circuit synthesis is essential for optimizing limited qubit resources and mitigating noise effects. Quantum Linear Reversible Circuits (QLRCs) are a fundamental class of circuits with applications in quantum compilation or quantum error correction. They are composed exclusively of CX and SWAP gates, which are among the noisiest operations on current quantum hardware. Therefore, their efficient synthesis is pivotal for executing QLRCs on NISQ processors, which have restricted connectivity between qubits. In this direction, we introduce a Reinforcement Learning (RL)-based synthesis approach using Proximal Policy Optimization (PPO) to synthesize QLRCs on generic topologies of up to five qubits. This work extends previous work that did not handle different topologies of quantum processors. Our method dynamically adapts to hardware constraints, learning optimal or near-optimal gate decompositions. We compare our approach against Qiskit’s synthesis methods for QLRCs, demonstrating that our RL-based synthesizer consistently achieves lower CX gate depth. These results highlight the potential of RL-driven quantum circuit synthesis as a powerful alternative to traditional heuristic-based techniques, paving the way for more efficient AI-based quantum compilation strategies in the NISQ era.

Massive Open Online Courses (MOOCs) represent an accessible and user-friendly tool for disseminating innovative and cutting-edge topics to broad segments of civil society via online learning platforms, enabling users to learn at their own pace and on their own schedule. In this contribution, we describe the design and the implementation of a Massive Open Online Course on Parallel Computing and High-Performance Computing, developed for Federica Web Learning: the University Center for innovation, experimentation, and dissemination of multimedia teaching at the University of Naples Federico II.

Synthetic Aperture Radar (SAR) tomography is an advanced technique for monitoring deformations of the Earth’s surface. However, the computational complexity of SAR tomography algorithms often restricts their application to large-scale datasets. To address this issue, we introduce a multi-level parallel implementation of a single scatterer detection algorithm specifically designed to exploit the capabilities of modern heterogeneous High-Performance Computing (HPC) systems. By efficiently distributing the computational workload at different levels across multiple processing units, our parallel approach significantly reduces processing time, facilitating the analysis of extensive SAR datasets. We assess the performance of our parallel implementation using real-world SAR data, showcasing its effectiveness in enhancing both the efficiency and scalability of SAR tomography. Our work contributes to advancing remote sensing techniques and offers valuable insights into the application of HPC for large-scale environmental monitoring.

Summary This special issue on the Pervasive Nature of HPC (PN‐HPC) collects an extension of the most valuable works presented at the sixth Workshop on Models, Algorithms and Methodologies for Hybrid Parallelism in New HPC Systems (MAMHYP‐22), held in Gdansk (Poland) in September 2022, jointly with the 14th conference on Parallel Processing and Applied Mathematics (PPAM‐22). New original papers related to the workshop themes are also included. The final aim is to provide a glimpse of the current state of knowledge related to the development of efficient methodologies and algorithms for HPC systems with multiple forms of parallelism.

Data crowdsourcing is an increasingly pervasive and lifestyle-changing technology due to the flywheel effect that results from the interaction between the Internet of Things and Cloud Computing. This paper presents the Citizen Science for the Sea with Information Technologies (C4Sea-IT) framework. It is an open platform for gathering marine data from leisure boat instruments. C4Sea-IT aims to provide a coastal marine data gathering, moving, processing, exchange, and sharing platform using the existing navigation instruments and sensors for today's leisure and professional vessels. In this work, a use case for the detection and tracking of marine litter is shown. The final goal is weather/ocean forecasts argumentation with Artificial Intelligence prediction models trained with crowdsourced data.

On behalf of the Organizing Committee, we welcome you to the 31st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP2023), organized by the Department of Science and Technology of the University of Naples “Parthenope”. The conference was hosted in Naples in the prestigious Villa Doria d'Angri from the 1st to the 3rd of March 2023.

Welcome to the 31st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP2023).

While using High-Performance Computing (HPC) for precise and accurate air quality forecasts is a common issue, similar services devoted to marine pollution in coastal areas remain challenging. This paper presents Water quality Community Model Plus Plus (WaComM++) leveraging a parallelization schema enabling the users to run it on heterogeneous parallel architectures. We evaluated the proposed model under several execution approaches using a real-world application for pollutants forecast in the Gulf of Napoli (Campania, Italy). As a result, WaComM++ has produced results 657K times faster than the sequential run (taking into account the Particles' Outer Cycle and not considering the particle domain distribution) when using distributed and shared memory with multi-GPUs dealing with about 25 million particles.

In this paper, the Shoreline Alert Model (SAM) is presented as a component of a computation platform based on workflows dedicated to extreme weather/marine event simulation. The model aims to mitigate the effects of global change by providing decision-makers, scientists, and engineers with a novel, next-generation tool set for facing extreme weather events and implementing related management or emergency responses. SAM uses a parallelization schema, allowing users to run it on heterogeneous parallel architectures. As a result, SAM produces approximately 24 times faster results than the baseline when using shared memory with distributed memory and dealing with about 20,000 transects along the Campania coastline. The system is based on the algorithms of the open-source numerical models WRF (Weather Research and Forecasting) and WW3 (Wave-watch III) implemented with refraction and shoaling routines together with run-up equations to form the modeling chain used for coastal flooding assessment.

Clustering algorithms are efficient tools for discov-ering correlations or affinities within large datasets and are the basis of several Machine Learning processes based on data generated by sensor networks. Recently, such algorithms have found an active application area closely correlated to the Edge Computing paradigm. The final aim is to transfer intelligence and decision-making ability near the edge of the networks to detect or prevent, as an example, attacks from insecure domains. In such a context, the present work introduces a new hybrid clustering algorithm for Edge Computing environments that can classify edge nodes taking into account their reliability. The algorithm is later evaluated from the points of view of the performance and energy consumption, comparing it with two high -end G PU - based computing systems. The achieved results confirm the possibility of designing intelligent sensors networks where decisions are taken at the data collection points.

The use of hardware accelerators, based on code and data offloading devoted to overcoming the CPU limitations in cores, is one of the main distinctive trends in high-end computing and related applications in the last decade. However, while code offloading is convenient for performance improvement, becoming a commonly used paradigm, memory access and management are a source of bottlenecks due to the need to interact with different address spaces. In this regard, NVidia introduced the CUDA Unified Memory model to avoid explicit memory copies between the machine hosting the accelerator device and the device itself and vice-versa. This paper shows a novel design and implementation of the support to the CUDA Unified Memory in open-source GPGPU virtualization services. The performance evaluation demonstrates that the overhead due to the virtualization and remoting is acceptable considering the possibility of sharing CUDA-enabled GPUs between various and heterogeneous machines hosted at the edge, in cloud infrastructures, or as accelerator nodes in an HPC scenario. A prototype implementation of the proposed solution is available as open-source.

Clustering algorithms are efficient tools for discovering correlations or affinities within large datasets and are the basis of several Artificial Intelligence processes based on data generated by sensor networks. Recently, such algorithms have found an active application area closely correlated to the Edge Computing paradigm. The final aim is to transfer intelligence and decision-making ability near the edge of the sensors networks, thus avoiding the stringent requests for low-latency and large-bandwidth networks typical of the Cloud Computing model. In such a context, the present work describes a new hybrid version of a clustering algorithm for the NVIDIA Jetson Nano board by integrating two different parallel strategies. The algorithm is later evaluated from the points of view of the performance and energy consumption, comparing it with two high-end GPU-based computing systems. The results confirm the possibility of creating intelligent sensor networks where decisions are taken at the data collection points.

Summary This work is a part of the global tendency to use modern computing systems for modeling the phase‐field phenomena. The main goal of this article is to improve the performance of a parallel application for the solidification modeling, assuming the dynamic intensity of computations in successive time steps when calculations are performed using a carefully selected group of nodes in the grid. A two‐step method is proposed to optimize the application for multi‐/manycore architectures. In the first step, the loop fusion is used to execute all kernels in a single nested loop and reduce the number of conditional operators. These modifications are vital to implementing the second step, which includes an algorithm for the dynamic workload prediction and load balancing across cores of a computing platform. Two versions of the algorithm are proposed—with the 1D and 2D maps used for predicting the computational domain within the grid. The proposed optimizations allow increasing the application performance significantly for all tested configurations of computing resources. The highest performance gain is achieved for two Intel Xeon Platinum 8180 CPUs, where the new code based on the 2D map yields the speedup of up to 2.74 times, while the usage of the proposed method with the 2D map for a single KNL accelerator permits reducing the execution time up to 1.91 times.

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Summary In this paper, we introduce an adaptive procedure for the numerical computation of a high‐dimensional integrals on HPC systems with heterogeneous nodes composed of multi‐core CPU and GPU devices. To this aim, we have integrated together two different approaches: a first one is in charge of a fair workload among the threads running on the multi‐core CPU, while a second one is in charge of an efficient execution of the computational kernels on the GPU. We tested the resulting algorithm on several test functions on a system where the nodes are provided with two Intel ten‐core CPU and one NVIDIA GPU device.

Concurrent data structures are widely used in many software stack levels, ranging from high level parallel scientific applications to low level operating systems. The key issue of these objects is their concurrent use by several computing units (threads or process) so that the design of these structures is much more difficult compared to their sequential counterpart, because of their extremely dynamic nature requiring protocols to ensure data consistency, with a significant cost overhead. At this regard, several studies emphasize a tension between the needs of sequential correctness of the concurrent data structures and scalability of the algorithms, and in many cases it is evident the need to rethink the data structure design, using approaches based on randomization and/or redistribution techniques in order to fully exploit the computational power of the recent computing environments. The problem is grown in importance with the new generation High Performance Computing systems aimed to achieve extreme performance. It is easy to observe that such systems are based on heterogeneous architectures integrating several independent nodes in the form of clusters or MPP systems, where each node is composed by powerful computing elements (CPU core, GPUs or other acceleration devices) sharing resources in a single node. These systems therefore make massive use of communication libraries to exchange data among the nodes, as well as other tools for the management of the shared resources inside a single node. For such a reason, the development of algorithms and scientific software for dynamic data structures on these heterogeneous systems implies a suitable combination of several methodologies and tools to deal with the different kinds of parallelism corresponding to each specific device, so that to be aware of the underlying platform. The present work is aimed to introduce a scalable model to manage a special class of dynamic data structure known as heap based priority queue (or simply heap) on these heterogeneous architectures. A heap is generally used when the applications needs set of data not requiring a complete ordering, but only the access to some items tagged with high priority. In order to ensure a tradeoff between the correct access to high priority items by the several computing units with a low communication and synchronization overhead, a suitable reorganization of the heap is needed. More precisely we introduce a unified scalable model that can be used, with no modifications, to redeploy the items of a heap both in message passing environments (such as clusters and or MMP multicomputers with several nodes) as well as in shared memory environments (such as CPUs and multiprocessors with several cores) with an overhead independent of the number of computing units. Computational results related to the application of the proposed strategy on some numerical case studies are presented for different types of computing environments.

Summary Heterogeneous architectures seem to be not only the present but also the future of the HPC world (eg, see the Exascale Project of U.S. Department of Energy or the European Horizon 2020 FET Proactive ‐ High Performance Computing Call). A lot of work has been done in developing software libraries useful to solve problem described by linear equations on such computing systems. Instead, not the same effort is spent in such context for the implementation of software modules to be used to solve non‐linear problem. In this work, we present some experiences related with the implementation of a Quasi‐Newton method able to exploit, using a combination of “Task Scheduling,” “matrix‐free,” and “look‐ahead” approaches, both the CPUs and the GP‐GPUs components of a heterogeneous system.

Models, algorithms, and tools for highly heterogeneous computing environments

Summary Low‐power devices are usually highly constrained in terms of CPU computing power, memory, and GPGPU resources for real‐time applications to run. In this paper, we describe RAPID, a complete framework suite for computation offloading to help low‐powered devices overcome these limitations. RAPID supports CPU and GPGPU computation offloading on Linux and Android devices. Moreover, the framework implements lightweight secure data transmission of the offloading operations. We present the architecture of the framework, showing the integration of the CPU and GPGPU offloading modules. We show by extensive experiments that the overhead introduced by the security layer is negligible. We present the first benchmark results showing that Java/Android GPGPU code offloading is possible. Finally, we show the adoption of the GPGPU offloading into BioSurveillance, a commercial real‐time face recognition application. The results show that, thanks to RAPID, BioSurveillance is being successfully adapted to run on low‐power devices. The proposed framework is highly modular and exposes a rich application programming interface to developers, making it highly versatile while hiding the complexity of the underlying networking layer.

In this paper we are concerned with improvements and enhancements of a medical imaging grid-enabled infrastructure, named MedIGrid, oriented to the transparent use of resource-intensive applications for managing, processing and visualizing biomedical images. We describe an implementation of the MedIGrid PSE in an LCG/gLite environment. We’ll mainly focus on how to exploit the features of the new middleware environment to improve the efficiency and the services reliability of the PSE; further, some comments will be devoted to how to modify, extend and/or improve the underlying numerical components.

Abstract In this paper we discuss the problem of computing a multidimensional integral on a MIMD distributed‐memory multiprocessor. Adaptive quadrature is known as a good approach to the problem of achieving accuracy and reliability while attempting to minimize the number of function evaluations. The implementation makes use of dynamical data structures able to manage subinterval partition. On a distributed‐memory multiprocessor, each processor is able to execute code and to manipulate data structures in its own local memory only, and data are sent from one processor to another one by explicit message‐passing. Efficient implementation of an adaptive algorithm for the multidimensional quadrature on a parallel computer is quite difficult, because of the need for continuous information exchange between processors. Our algorithm is based on a global adaptive strategy which dynamically balances the workload and reduces the data communication between processors in order to use the message‐passing environment efficiently. The results and timings for several tests are given.