Vertica is a column-oriented relational database management system built on massively parallel processing architecture. Rather than a traditional, monolithic implementation of materialized view, Vertica instead provides two separate features, flattened tables and live aggregation projections. These features not only support the basic functionality of materialized views, but also provide flexibility and consistency beyond the traditional materialized view implementation. Flattened tables contain denormalized columns whose main purpose is to materialize pre-computed joins with other tables. Live aggregate projections are an always up-to-date layer built on top of individual tables, including flattened tables, which maintain real-time summaries of table contents. This paper will present the main architecture of these two features, discuss how they differ from traditional materialized views, and how they take advantage of Vertica's architecture to achieve high performance. Experimental results with TPC-DS benchmarks will be provided to demonstrate the claimed performance benefit.

In this paper we present a completely on-chip voltage regulation technique which promises to adjust the degree of voltage regulation in a digital logic chip in the face of process induced delay variations so as to minimize energy dissipation while always guaranteeing the target operatingfrequency. For this purpose the delay of a critical path replica of the circuit being regulated is constantly compared with the target delay provide the regulator with the information needed to select the optimum voltage levels. The proposed solution is even more attractive in that no external components are required. Based on this scheme, a completely on-chip voltage regulator has been fabricated in a commercial 0.5μm CMOS process and used to generate the inner rail voltages for a DSP multiplier-accumulator (MAC) implemented in mixed swing QuadRail. Measured results indicate that the voltages generated by the regulator offer a very high degree of load regulation thus verifying the fast response time of the on-chip output buffer.

This paper describes a completely on-chip voltage regulation technique for locally generating an adaptive low voltage power supply rail from a given higher voltage power supply without requiring any external component.The on-chip regulator, based on delay servoing, primarily comprises of a critical path replica, charge pump and a high performance voltage buffer which is the most critical component of the design.Simulation results in OSl.trn CMOS process demonstrate that the buffer offers a low DC output impedance, a high degree of voltage regulation (output ripple of 12% of Vdd) and a superior line regulation (upto the maximum clock frequency of SOMHz) even under strongly varying load conditions.The regulator response for a typical worst case load exhibits a maximum voltage fluctuation of 4% of Vdd with a reasonably fast response time.

One of the major problems faced by the designer when operating CMOS static logic circuits at low power supply voltages (normalized to VT is that the delay spread introduced by today's IC manufacturing variations can increase dramatically. In this paper we describe an approach for decreasing the delay spread and power spread in ICs based on adaptively servoing the circuits between static CMOS operation and QuadRail operation. An on-chip series-regulator employing a dummy delay path is used to generate the adaptive low swing power supply rails making this approach fully compatible with a standard CMOS IC design methodology. Simulation results are presented demonstrating that for a 16*16+36-bit multiplier-accumulator designed in 0.5µm CMOS process the proposed approach decreases the delay spread from 3.9X to 2.3X and the power spread from 3.6X to 1.8X.