The verification of embedded software has become an important subject over the last years. However, neither standalone verification approaches, like simulation-based or formal verification, nor state-of-the-art hybrid/semiformal verification approaches are able to verify large and complex embedded software with hardware dependencies. This work presents a new scalable and extendable hybrid verification approach for the verification of temporal properties in embedded software with hardware dependencies using for the first time a new mixed bottom-up/top-down algorithm. Therefore, new algorithms and methodologies like static parameter assignment and counterexample guided simulation are proposed in order to combine simulation-based and formal verification in a new way. We have successfully applied this hybrid approach to embedded software applications: Motorola's Powerstone Benchmark suite and a complex industrial embedded automotive software. The results show that our approach scales better than stand-alone software model checkers to reach deep state spaces. The whole approach is best suited for fast falsification.

In this paper a comprehensive assertion-based verification methodology for the digital, analog and software domain of heterogeneous systems is presented. The proposed methodology combines a novel mixed-signal assertion language and the corresponding automatic verification algorithm. The algorithm translates the heterogeneous temporal properties into observer automata for a semi-formal verification. This enables automatic verification of complex heterogeneous properties that can not be verified by existing approaches. The experimental results show the integration of mixed-signal assertions into a simulation environment and demonstrate the broad applicability and the high value of the evolved solution.

The verification of embedded software has become an important subject over the last years. This work presents a new semiformal verification approach called SofTPaDS. It combines assertion-based and symbolic simulation approaches for the verification of embedded software with hardware dependencies. SofTPaDS shows to be more efficient than the software model checkers in order to trace deep state spaces and improves the state coverage relative to a simulation-based verification tool. We have successfully applied our approach to an industrial automotive embedded software.

The amount of software in embedded systems has increased significantly over the last years and, therefore, the verification of embedded software is of fundamental importance. One of the main problems in embedded software is to verify variables and functions based on temporal properties. Formal property verification using model checker often suffers from the state space explosion problem when a large software design is considered. In this paper, we propose two new approaches to integrate assertions in the verification of embedded software using simulation-based verification. Firstly, we extended a SystemC hardware temporal checker with interfaces in order to monitor the embedded software variables and functions that are stored in a microprocessor memory model. Secondly, we derived a SystemC model from the original C program in order to integrate directly with the SystemC temporal checker. We performed a case study on an embedded software from automotive industry which is responsible for controlling read and write requests to a non-volatile memory.

Symbolic property verification is an increasingly popular debugging method based on Binary Decision Diagrams (BDDs). The lack of optimization of the state space search is often responsible for the excessive growth of the BDDs. In this paper we present an accelerated symbolic property verification by means of a new guiding technique that automatically finds the set of interesting variables by exploiting the property and the transition relation of a design. Our property based state space guiding can substantially speed up the verification process. The heuristic picks up the interesting state or the input variables automatically and utilizes them in guiding the state space traversal. This guiding approach is a novel one as it is automatic, efficient and stable for fast falsification. Furthermore it does not degrade as much for full validation.

Formal verification has become an alternative to simulation for the validation of systems. In particular, temporal logic model checking of finite state machines is a widely accepted verification technique. It automatically proves the correctness of design specifications. There exist several approaches extending model checking for the verification of timed systems. Things become more complex if additional multivalued signals are added to the systems. In this constellation, time effects and data dependencies merge. Therefore, a stand-alone model checking approach is in many cases not sufficient for verification, especially if extreme values of signals have to be determined. We extend an existing real-time finite state model by multivalued signals (ranges, enumerations and bit vectors). We present algorithms for computing minimal and maximal values of signals in specified states or within certain time bounds. We show the practicability of our approach by means of a case study.

We present a rigorous but transparent semantics definition of SystemC that covers method, thread, and clocked thread behavior as well as their interaction with the simulation kernel process. The semantics includes watching statements, signal assignment, and wait statements as they are introduced in SystemC V1.O. We present our definition in form of distributed Abstract State Machines (ASMs) rules reflecting the view given in the SystemC User's Manual and the reference implementation. We mainly see our formal semantics as a concise, unambiguous, high-level specification for SystemC-based implementations and for standardization. Additionally, it can be used as a sound basis to investigate SystemC interoperability with Verilog and VHDL.

The verification of digital designs, i.e., hardware or embedded hardware/software systems, is an important task in the design process. Often more than 70% of the development time is spent for locating and correcting errors in the design. Therefore, many techniques have been proposed to support the debugging process. Recently, simulation and test methods have been accompanied by formal methods such as equivalence checking and property checking. However their industrial applicability is currently restricted to small or medium sized designs or to a specific phase in the design cycle. In this paper, we present a method for verifying temporal properties of systems described in an executable description language. Our method allows the user to specify properties about the system in finite linear time temporal logic. These properties are translated to a special kind of finite state machines which are then efficiently checked on-the-fly during each simulation run. Properties may be placed anywhere in the system description and violations are immediately indicated to the designer.

Temporal logic model checking is a technique for the automatic verification of systems against specifications. Besides the correctness of safety and liveness properties it is often important to determine critical answer and delay times of systems, especially if they are embedded in a real-time environment. In this paper we present an approach which allows the verification as well as the timing analysis of real-time systems. The systems are described as networks of communicating time-extended finite state machines (I/O-interval structures). We use a compact symbolic representation to obtain efficient analysis algorithms.