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William Jao

dblp:12/7009 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1998
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 77% Integrated circuit design · 23%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › logic synthesis › circuit optimization
arithmetic circuit optimization
0.011998
Circuit optimization using carry-save-adder cells · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998
Electronic design automation › high-level synthesis
arithmetic-level optimization
0.011998
Arithmetic Optimization Using Carry-Save-Adders · DAC 1998
Electronic design automation
high-level synthesis
0.011998
Arithmetic Optimization Using Carry-Save-Adders · DAC 1998
Electronic design automation
logic synthesis
0.011998
Circuit optimization using carry-save-adder cells · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998
Integrated circuit design
digital circuit design
0.021998
Circuit optimization using carry-save-adder cells · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998
Arithmetic Optimization Using Carry-Save-Adders · DAC 1998
Integrated circuit design › digital system design
register-transfer level design
0.021998
Circuit optimization using carry-save-adder cells · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998
Arithmetic Optimization Using Carry-Save-Adders · DAC 1998

Methods — techniques the papers use, named apart from their topics

operation-split · 0.0operation-duplication · 0.0
YearPublicationVenuePosition
1998 Arithmetic Optimization Using Carry-Save-Adders
abstract
Carry-save-adder(CSA) is the most often used type of operation in implementing a fast computation of arithmetics of register-transfer level design in industry. This paper establishes a relationship between the properties of arithmetic computations and several optimizing transformations using CSAs to derive consistently better qualities of results than those of manual implementations. In particular, we introduce two important concepts, operation-duplication and operation-split, which are the main driving techniques of our algorithm for achieving an extensive utilization of CSAs. Experimental results from a set of typical arithmetic computations found in industry designs indicate that automating CSA optimization with our algorithm produces designs with significantly faster timing and less area.
Taewhan Kim 0001, William Jao, Steven W. K. Tjiang
DAC2
1998 Circuit optimization using carry-save-adder cells
abstract
Carry-save-adder (CSA) is the most often used type of operation in implementing a fast computation of arithmetics of register-transfer-level design in industry. This paper establishes a relationship between the properties of arithmetic computations and several optimizing transformations using CSAs to derive consistently better qualities of results than those of manual implementations. In particular, we introduce two important concepts, operation duplication and operation split, which are the main driving techniques of our algorithm for achieving an extensive utilization of CSAs. Experimental results from a set of typical arithmetic computations found in industry designs indicate that automating CSA optimization with our algorithm produces designs with up to 53% faster timing and up to 42% smaller area.
Taewhan Kim 0001, William Jao, Steven W. K. Tjiang
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2