Dynamic optical interconnects using fast Optical Circuit Switches (OCS) are emerging as a scalable and energy efficient alternative to increasing network demands. Initial concerns regarding slow switching speeds of OCSs were recently overcome, with prototypes enabling circuit setup in a few microseconds. This can potentially broaden the classes of traffic patterns that can be carried efficiently by an alloptical interconnect. However, application performance on such newer interconnects has not been fully understood yet. In this paper, we explore the the gap between advances in faster OCS hardware and the potential success of such newer technologies in terms of application performance and cluster energy efficiency. We evaluate the performance of latencysensitive distributed applications running on a fast OCS environment, analyzing its impact to overall server and network energy efficiency. We also discuss scheduling inefficiencies of current fast OCSs and evaluate ideas to solve them. We find that while some distributed applications suffer minimal performance penalty when running on fast OCSs, more flexible schedulers, like the ones outlined in this paper, improve application performance and OCS efficiency by up to 2.44 times compared to the strategies in the literature. Dynamic optical interconnects using fast Optical Circuit Switches (OCS) are emerging as a scalable and energy efficient alternative to increasing network demands. Initial concerns regarding slow switching speeds of OCSs were recently overcome, with prototypes enabling circuit setup in a few microseconds. This can potentially broaden the classes of traffic patterns that can be carried efficiently by an all-optical interconnect. However, application performance on such newer interconnects has not been fully understood yet. In this paper, we explore the the gap between advances in faster OCS hardware and the potential success of such newer technologies in terms of application performance and cluster energy efficiency. We evaluate the performance of latency-sensitive distributed applications running on a fast OCS environment, analyzing its impact to overall server and network energy efficiency. We also discuss scheduling inefficiencies of current fast OCSs and evaluate ideas to solve them. We find that while some distributed applications suffer minimal performance penalty when running on fast OCSs, more exible schedulers, like the ones outlined in this paper, improve application performance and OCS efficiency by up to 2.44 times compared to the strategies in the literature.

Optical circuit switches (OCS) are emerging as a solution to the high bandwidth demands of data center networks. Recent research prototypes provide scalable bandwidth using a tenth or less of the power of an Electronic Packet Switch (EPS) and - unlike traditional OCSs - are able to provision point-to-point circuits in a few μs. The disadvantage of OCS is the lack of efficient buffers to store and process packets, requiring routing decisions (i.e. circuit scheduling) to be performed by an external controller. Thus, application performance using an optical data plane depends on the controller adopted. The problem is that exploring the technology to evaluate its advantages as well as comparing different controllers is a prohibitive task, restricted to few research groups. Fast OCS technology is still in its early stages, and studying the viability of its adoption requires building OCS prototypes, an expensive and time consuming solution. To address this problem we designed OCSEMU, a distributed emulation platform that mimics the behavior of fast OCSs using traditional packet switches. We show that OCSEMU achieves comparable performance to the state-of-the-art OCS prototype, providing the extensibility necessary to explore application performance and optimizations of emerging optical interconnects.

Recent proposals have employed optical circuit switching (OCS) to reduce the cost of data center networks. However, the relatively slow switching times (10--100 ms) assumed by these approaches, and the accompanying latencies of their control planes, has limited its use to only the largest data center networks with highly aggregated and constrained workloads. As faster switch technologies become available, designing a control plane capable of supporting them becomes a key challenge.

This article introduces McPAT, an integrated power, area, and timing modeling framework that supports comprehensive design space exploration for multicore and manycore processor configurations ranging from 90nm to 22nm and beyond. At microarchitectural level, McPAT includes models for the fundamental components of a complete chip multiprocessor, including in-order and out-of-order processor cores, networks-on-chip, shared caches, and integrated system components such as memory controllers and Ethernet controllers. At circuit level, McPAT supports detailed modeling of critical-path timing, area, and power. At technology level, McPAT models timing, area, and power for the device types forecast in the ITRS roadmap. McPAT has a flexible XML interface to facilitate its use with many performance simulators. Combined with a performance simulator, McPAT enables architects to accurately quantify the cost of new ideas and assess trade-offs of different architectures using new metrics such as Energy-Delay-Area2 Product (EDA2P) and Energy-Delay-Area Product (EDAP). This article explores the interconnect options of future manycore processors by varying the degree of clustering over generations of process technologies. Clustering will bring interesting trade-offs between area and performance because the interconnects needed to group cores into clusters incur area overhead, but many applications can make good use of them due to synergies from cache sharing. Combining power, area, and timing results of McPAT with performance simulation of PARSEC benchmarks for manycore designs at the 22nm technology shows that 8-core clustering gives the best energy-delay product, whereas when die area is taken into account, 4-core clustering gives the best EDA2P and EDAP.

Among power dissipation components, leakage power has become more dominant with each successive technology node. Leakage energy waste can be reduced by power gating. In this paper, we extend token-based adaptive power gating (TAP), a technique to power gate an actively executing core during memory accesses, to many-core Chip Multi-Processors (CMPs). TAP works by tracking every system memory request and its estimated time of arrival so that a core may power gate itself without performance or energy loss. Previous work on TAPshows several benefits compared to earlier state-of-the-art techniques, including zero performance hit and 2.58 times average energy savings for out-of-order cores. We show that TAP can adapt to increasing memory contention by increasing power-gated time by 3.69 times compared to a low memory-pressure case. We also scale TAP to many-core architectures with a distributed wake-up controller that is capable of supporting staggered wake-ups and able to power gate each core for 99.07% of the time, achieved by a non-scalable centralized scheme.

In mobile systems, the problems of short battery life and increased temperature are exacerbated by wasted leakage power. Leakage power waste can be reduced by power-gating a core while it is stalled waiting for a resource. In this work, we propose and model memory access power gating (MAPG), a low-overhead technique to enable power gating of an active core when it stalls during a long memory access. We describe a programmable two-stage power gating switch design that can vary a core's wake-up delay while maintaining voltage noise limits and leakage power savings. We also model the processor power distribution network and the effect of memory access power gating on neighboring cores. Last, we apply our power gating technique to actual benchmarks, and examine energy savings and overheads from power gating stalled cores during long memory accesses. Our analyses show the potential for over 38% energy savings given “perfect” power gating on memory accesses; we achieve energy savings exceeding 20% for a practical, counter-based implementation.

We propose a low-overhead technique, Token-Based Adaptive Power Gating (TAP), to power gate an actively executing out-of-order core during memory accesses. TAP tracks every system memory request, providing a lower-bound estimate for the response time. TAP also tracks the state of every power-gateable core in the system, to provide minimal latency wake-up modes to cores such that voltage noise safety margins are not violated. A power-gating switch that utilizes TAP can deterministically power gate its core with energy savings up to 22.39% and no performance hit.

This paper introduces McPAT, an integrated power, area, and timing modeling framework that supports comprehensive design space exploration for multicore and manycore processor configurations ranging from 90nm to 22nm and beyond. At the microarchitectural level, McPAT includes models for the fundamental components of a chip multiprocessor, including in-order and out-of-order processor cores, networks-on-chip, shared caches, integrated memory controllers, and multiple-domain clocking. At the circuit and technology levels, McPAT supports critical-path timing modeling, area modeling, and dynamic, short-circuit, and leakage power modeling for each of the device types forecast in the ITRS roadmap including bulk CMOS, SOI, and double-gate transistors. McPAT has a flexible XML interface to facilitate its use with many performance simulators. Combined with a performance simulator, McPAT enables architects to consistently quantify the cost of new ideas and assess tradeoffs of different architectures using new metrics like energy-delay-area2 product (EDA2P) and energy-delay-area product (EDAP). This paper explores the interconnect options of future manycore processors by varying the degree of clustering over generations of process technologies. Clustering will bring interesting tradeoffs between area and performance because the interconnects needed to group cores into clusters incur area overhead, but many applications can make good use of them due to synergies of cache sharing. Combining power, area, and timing results of McPAT with performance simulation of PARSEC benchmarks at the 22nm technology node for both common in-order and out-of-order manycore designs shows that when die cost is not taken into account clustering 8 cores together gives the best energy-delay product, whereas when cost is taken into account configuring clusters with 4 cores gives the best EDA2P and EDAP.