In this work, a solid-state direct time-of-flight (dToF) and adaptive beam-steering Light Detection and Ranging (LiDAR) system is proposed for machine learning (ML) based object detection. To leverage the capabilities of software and hardware, a co-optimization design from a neural network based algorithm to the architecture of transmitter, receiver and optical components is realized. Firstly, an object detection neural network is proposed for the depth-only input algorithm, which indicates the Region of Interest (ROI) in the illuminating field and gives hints of opened scan channels in the next two frames to decrease the total cost of the laser driver and sensor array. Next, the proposed network utilizes the Cross-Stage-Patrial (CSP) block to replace the residual structure in the backbone to achieve a lightweight performance and is implemented on the NVIDIA-Jetson to verify the system-level adaptive beam steering feature. To realize the smart working mode, a customized multi-channel and addressable TX is designed for adaptive and optical control to save power consumption and extend the ranging distance. At the same time, a 128×80 resolution RX which consists of Single-Photon Avalanche Diodes (SPADs) and column-wise Time-to-Digital Converter (TDC) is incorporated to capture the returned photons for combining sub-regions into an entire depth map. Next, to customize the specific scanning mechanism, for the optical setup, a cylindrical lens array is designed to reshape the laser beam, which matches the pattern of the transmitter to illuminate different targeted objects. Both the laser driver chip and the sensor chip with a 128×80 SPAD array are fabricated in the 180-nm Bipolar-CMOS-DMOS (BCD) process. Finally, the laser driver chip realizes the power of 5 W with an adjustable pulse width of 1.5 ns and the SPAD array integrates the depth accuracy of 5 cm at 15 m. Due to that the neural network realizes an accuracy up to 0.8, a low-power solid-state LiDAR prototype with adaptive beam steering is demonstrated.

This paper presents a high-speed and high-resolution On-Chip Oscilloscope (OCO) for Auto-Peak-Power Controller (APPC) and Peak-Current Detector in voltage mode Direct Time-of-Flight(DToF) driver. The OCO supports both optical input and electrical input, with front-end circuit of TIA and PGA respectively. The front-end circuit bandwidth is up to 2GHz to support 500ps pulse width detection. The optical input is for detecting VCSEL peak power, and feedback to the integrated Boost Converter to adjust VCSEL supply voltage to find the target peak optical power. The electrical input is for detecting the VCSEL peak current to avoid driver over-current, by preventing APPC from adapting to excessive peak current due to abnormal VCSEL or PD. The front-end circuit is followed by an 11-bit asynchronous logic SAR-ADC with up to 40MHz sampling rate. The OSC time accuracy is 6.6ps and detected pulse width is up to 12.8ns. The chip was fabricated in BCD180nm process. According to the test results, the measured waveform of OCO is comparable with commercial oscilloscope. By turning on the OCO-based APPC feature, the variation of optical power is controlled within 3% in the temperature range of 25-85°C.

This article presents a$4 \times 10$Gb/s low-noise adaptive optical receiver, utilizing a current-reuse architecture and channel crosstalk-remove techniques in 65-nm CMOS process. The receiver integrates a transimpedance amplifier (TIA), a continuous-time linear equalizer (EQ), high-gain and high-bandwidth limiting amplifiers, and a 50-$\Omega $output driver into a single die. The TIA employs a common-source-based pseudo-differential topology with input series inductive peaking and$g_{m}$-enhancement to improve bandwidth and noise performance. An automatic-gain-control loop scheme is presented which solves the bandwidth variation issue caused by variation of the TIA input impedance, across a large dynamic range of a small input to a maximum overload current. Multiple crosstalk reduction techniques are adopted to improve the channel isolation performance. The 850-nm vertical cavity surface emitting laser (VCSEL)-based full-link measurement results show that the optical receiver achieves$20.4~\mu \text{A}_{\mathrm {pp}}$sensitivity bit-error-rate (BER$ < 1\text{e}$-12) with a 200-fF photodiode, competitive with other prior CMOS-based TIAs. The crosstalk over different channels is also measured, demonstrating only a sensitivity penalty of 1 dB.