A hierarchical leakage fault analysis methodology is proposed for IDDQ (quiescent power supply current) testing of VLSI CMOS circuits. A software system, QUIETEST, has been developed on the basis of this methodology. The software can select a small number of test vectors for IDDQ testing from the provided functional test set. Therefore, the total test time for IDDQ measurements can be reduced significantly to make IDDQ testing of VLSI CMOS circuits feasible in a production test environment. For two VLSI circuits QUIETEST was able to select less than 1% of functional test vectors from the full test set for covering as many leakage faults as would be covered if IDDQ was measured upon the application of 100% of the vectors.>

A complete analysis of the bridging faults between gate outputs in FC (full complementary) MOS and PE (precharge evaluate) MOS is presented. It is shown that circuit design to force wired-AND or wired-OR effects in the presence of bridging faults leads to an adverse effect on noise margin, area, and speed. Hence, a functional testing is not desirable if FC MOS gates are employed, and the alternative method involving current testing should be used. In PE MOS gates, however, current testing is not possible, and, therefore, functional testing must be resorted to, despite the adverse side effects. The authors consider an area-efficient implementation of PLAs (programmable logic arrays) which uses both FC MOS and PE MOS logic, an implementation that is commonly used in VLSI designs. All possible classes of bridging faults in this implementation are identified and methods of detecting them are given.>

A built-in self-test (BIST) design method for large embedded CMOS folded programmable logic arrays (PLAs) is presented that is based on a deterministic, function-independent structural method. It requires about half the testing time and comparable area overhead of deterministic BIST methods applied to corresponding nonfolded PLAs. Tests to detect stuck-at, bridging, cross-point and stuck-open faults are given.>

A compaction algorithm is presented that takes advantage of the fact that repeating patterns in the simulation output of microprocessors and microcontrollers occur due to specific reasons. An instance of each different, multiply-occurring repeating pattern is extracted as a subroutine in an efficient manner, as compared to the ad hoc approaches used earlier. Compaction is then achieved by replacing the repeating patterns by calls to appropriate subroutines. The algorithm has been implemented in a C program, with excellent results obtained. A sample of the results is included.>

ITTAP is a testability analysis program developed at the ITT-LSI technology center. In this paper we describe a testability measure for the test length and discuss the use of the selective trace concept for testability calculations. It is shown that ITTAP provides an order of magnitude improvement in run time over existing programs like SCOAP.