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Anton V. Gorshkov

dblp:120/0546 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2019
0000-0003-4568-0778ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 61% GPUs and heterogeneous computing · 30% Hardware accelerators and domain-specific architectures · 9%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation › program instrumentation
binary instrumentation
0.412019
GPU Instruction Hotspots Detection Based on Binary Instrumentation Approach · IEEE Trans. Computers 2019
GPUs and heterogeneous computing › GPU computing
GPU profiling
0.412019
GPU Instruction Hotspots Detection Based on Binary Instrumentation Approach · IEEE Trans. Computers 2019
Performance modeling and evaluation
profiling
0.412019
GPU Instruction Hotspots Detection Based on Binary Instrumentation Approach · IEEE Trans. Computers 2019

Methods — techniques the papers use, named apart from their topics

static and runtime information combination · 0.4binary instrumentation · 0.4
YearPublicationVenuePosition
2019 GPU Instruction Hotspots Detection Based on Binary Instrumentation Approach
abstract
The problem of profiling a compute kernel running on the CPU is mostly solved with the help of technologies that explore a code behavior in detail. But with a last decade trend when computation spreads to other devices, more power and performance efficient, we face a high need for fine-grain code profiling on such devices. Traditional methods are not always sufficient: program counter sampling requires special hardware support, and performance simulation works slowly. In this paper, we introduce a novel method for instruction hotspots detection based on the binary instrumentation approach and demonstrate it on Intel® Graphics. This method relies on three key principles: measurement with instruction block granularity, conscious placement of probes, and combination of static and runtime information. We demonstrate its ability to highlight the hottest instructions and lines of code, and its relatively low runtime overhead comparable to a native run. The method is applicable to GPUs and accelerators with in-order architecture, and could be used in a rapidly growing segment of accelerator solutions for computer vision and artificial intelligence.
Anton V. Gorshkov, Michael Berezalsky, Julia Fedorova, Konstantin Levit-Gurevich, Noam Itzhaki
IEEE Trans. Computers1