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Vincent Immler

dblp:120/1045 · DBLP profile ↗
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5ranked-venue papers
1as first author
2since 2021 · last 2025
0000-0002-1299-2823ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 3 · 1 first-author · 1 since 2021Systems, architecture and hardware · 2 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
3 papers
Hardware security and side channels · 100%
Computer architecture, parallel and distributed computing, and storage systems
3 papers
Integrated circuit design · 50% Electronic design automation · 50%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels › hardware security primitives
physical unclonable function
0.312018
A measurement system for capacitive PUF-based security enclosures · DAC 2018
Hardware security and side channels › side-channel attack
electromagnetic side channel
0.312017
Your Rails Cannot Hide from Localized EM: How Dual-Rail Logic Fails on FPGAs · CHES 2017
Hardware security and side channels
side-channel attack
0.312017
Your Rails Cannot Hide from Localized EM: How Dual-Rail Logic Fails on FPGAs · CHES 2017
Integrated circuit design › asynchronous circuit design
dual-rail logic
0.312017
Your Rails Cannot Hide from Localized EM: How Dual-Rail Logic Fails on FPGAs · CHES 2017
Hardware security and side channels
side-channel countermeasures
0.212014
Early Propagation and Imbalanced Routing, How to Diminish in FPGAs · CHES 2014
Electronic design automation › physical design › routing
FPGA routing
0.212014
Early Propagation and Imbalanced Routing, How to Diminish in FPGAs · CHES 2014
Electronic design automation › physical design › routing
routing congestion
0.212014
Early Propagation and Imbalanced Routing, How to Diminish in FPGAs · CHES 2014
Integrated circuit design
analog and mixed-signal circuits
0.112018
A measurement system for capacitive PUF-based security enclosures · DAC 2018

Methods — techniques the papers use, named apart from their topics

digital lock-in amplifier · 0.7differential capacitive measurement · 0.7
YearPublicationVenuePosition
2025 Ultra-Compact and High-Throughput True Random Number Generator for FPGAs
Gabriel Cojocaru, Vincent Immler
ACM Great Lakes Symposium on VLSI2
2023 Analysis of Arbitrary Waveform Generation for Voltage Glitches
abstract
Voltage glitches are a fault injection technique that aim at disrupting the power supply such that the data or instruction flow in a chip can be modified. In 2019, a new class of voltage glitches was introduced based on arbitrary voltage supply waveforms that are generated by polynomial interpolation over randomly chosen points. Despite their demonstrated success in practical studies, many questions remained unanswered, e.g., what are the relevant characteristics of the waveform that enable this success? To answer this, we investigate the waveform generation process itself, prior to applying any type of automated search. In addition, we perform an in-depth analysis of (non-)working voltage glitches. Furthermore, we introduce the notion of specificity for glitches, by studying how waveforms can be generated that achieve very specific goals, such as a double instruction skip. We compare our results based on a real-world benchmark for firmware extraction and demonstrate that our insights lead to a reset/success ratio that is improved by a factor of 13.5 compared to previous work. This amplifies the threat of this class of voltage glitches.
Stanislav Lyakhov, Vincent Immler
FDTC2
2018 A measurement system for capacitive PUF-based security enclosures
abstract
Battery-backed security enclosures that are permanently monitored for penetration and tampering are common solutions for providing physical integrity to multi-chip embedded systems. This paper presents a well-tailored measurement system for a batteryless PUF-based capacitive enclosure. The key is derived from the PUF and encrypts the underlying system. We present a system concept for combined enclosure integrity verification and PUF evaluation. The system performs differential capacitive measurements inside the enclosure by applying stimulus signals with a 180° phase shift that isolate the local variation in the femtofarad range. The analog circuitry and corresponding digital signal processing chain perform precise PUF digitization, using a microcontroller-based digital lock-in amplifier. The system's measurement range is approximately ±73 fF, the conversion time per PUF node is less than 0.6 ms, and the raw data shows a measurement noise of 0.3 fF. This is the base for a high-entropy key generation while enabling a short system startup time. The system is scalable to the enclosure size and has been experimentally verified to extract information from 128 PUF nodes, using a system prototype. The results show that our concept forms a cornerstone of a novel batteryless PUF-based security enclosure.
Johannes Obermaier, Vincent Immler, Matthias Hiller, Georg Sigl
DAC2
2017 Your Rails Cannot Hide from Localized EM: How Dual-Rail Logic Fails on FPGAs
Vincent Immler, Robert Specht, Florian Unterstein
CHES1
2014 Early Propagation and Imbalanced Routing, How to Diminish in FPGAs
Amir Moradi 0001, Vincent Immler
CHES2