Nader Khammassi

dblp:120/1814 · DBLP profile ↗
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7ranked-venue papers
2as first author
1since 2021 · last 2022
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 7 · 2 first-author · 1 since 2021Software engineering, systems software and programming languages · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Emerging computing paradigms · 62% Performance modeling and evaluation · 32% Embedded and real-time systems · 3%

Topics — the 10 heaviest of 11, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms
quantum computer architecture
0.722019
eQASM: An Executable Quantum Instruction Set Architecture · HPCA 2019
An experimental microarchitecture for a superconducting quantum processor · MICRO 2017
Emerging computing paradigms › quantum computer architecture › quantum software stack
quantum instruction set
0.722019
eQASM: An Executable Quantum Instruction Set Architecture · HPCA 2019
An experimental microarchitecture for a superconducting quantum processor · MICRO 2017
Emerging computing paradigms › quantum control
quantum control microarchitecture
0.422019
An experimental microarchitecture for a superconducting quantum processor · MICRO 2017
eQASM: An Executable Quantum Instruction Set Architecture · HPCA 2019
Performance modeling and evaluation › profiling
communication profiling
0.312018
Memory and Communication Profiling for Accelerator-Based Platforms · IEEE Trans. Computers 2018
Performance modeling and evaluation › profiling
memory access profiling
0.312018
Memory and Communication Profiling for Accelerator-Based Platforms · IEEE Trans. Computers 2018
Performance modeling and evaluation
profiling
0.312018
Memory and Communication Profiling for Accelerator-Based Platforms · IEEE Trans. Computers 2018
Hardware accelerators and domain-specific architectures › accelerator architecture
accelerator-rich architecture
0.112018
Memory and Communication Profiling for Accelerator-Based Platforms · IEEE Trans. Computers 2018
Embedded and real-time systems
heterogeneous multi-core systems
0.112018
Memory and Communication Profiling for Accelerator-Based Platforms · IEEE Trans. Computers 2018
Emerging computing paradigms
quantum computing
0.112017
An experimental microarchitecture for a superconducting quantum processor · MICRO 2017
Emerging computing paradigms › quantum computing
superconducting qubit
0.112017
An experimental microarchitecture for a superconducting quantum processor · MICRO 2017

Methods — techniques the papers use, named apart from their topics

instrumentation · 0.3dynamic analysis · 0.3queue-based timing control · 0.3codeword-based event control · 0.3
YearPublicationVenuePosition
2022 OpenQL: A Portable Quantum Programming Framework for Quantum Accelerators
abstract
With the potential of quantum algorithms to solve intractable classical problems, quantum computing is rapidly evolving, and more algorithms are being developed and optimized. Expressing these quantum algorithms using a high-level language and making them executable on a quantum processor while abstracting away hardware details is a challenging task. First, a quantum programming language should provide an intuitive programming interface to describe those algorithms. Then a compiler has to transform the program into a quantum circuit, optimize it, and map it to the target quantum processor respecting the hardware constraints such as the supported quantum operations, the qubit connectivity, and the control electronics limitations. In this article, we propose a quantum programming framework named OpenQL, which includes a high-level quantum programming language and its associated quantum compiler. We present the programming interface of OpenQL, we describe the different layers of the compiler and how we can provide portability over different qubit technologies. Our experiments show that OpenQL allows the execution of the same high-level algorithm on two different qubit technologies, namely superconducting qubits and Si-Spin qubits. Besides the executable code, OpenQL also produces an intermediate quantum assembly code, which is technology independent and can be simulated using the QX simulator.
Nader Khammassi, Imran Ashraf 0002, Hans van Someren 0001, Razvan Nane, Anna M. Krol, M. Adriaan Rol, Lingling Lao, Koen Bertels, Carmen G. Almudéver
ACM J. Emerg. Technol. Comput. Syst.1
2019 eQASM: An Executable Quantum Instruction Set Architecture
abstract
A widely-used quantum programming paradigm comprises of both the data How and control How. Existing quantum hardware cannot well support the control How, significantly limiting the range of quantum software executable on the hardware. By analyzing the constraints in the control microarchitecture, we found that existing quantum assembly languages are either too high-level or too restricted to support comprehensive How control on the hardware. Also, as observed with the quantum microinstruction set QuMIS [1], the quantum instruction set architecture (QISA) design may suffer from limited scalability and Hexibility because of microarchitectural constraints. It is an open challenge to design a scalable and Hexible QISA which provides a comprehensive abstraction of the quantum hardware. In this paper, we propose an executable QISA, called eQASM, that can be translated from quantum assembly language (QASM), supports comprehensive quantum program How control, and is executed on a quantum control microarchitecture. With efficient timing specification, single-operation-multiple-qubit execution, and a very-long-instruction-word architecture, eQASM presents better scalability than QuMIS. The definition of eQASM focuses on the assembly level to be expressive. Quantum operations are configured at compile time instead of being defined at QISA design time. We instantiate eQASM into a 32-bit instruction set targeting a seven-qubit superconducting quantum processor. We validate our design by performing several experiments on a two-qubit quantum processor.
Xiang Fu 0003, Leon Riesebos, M. Adriaan Rol, Jeroen van Straten, Hans van Someren 0001, Nader Khammassi, Imran Ashraf 0002, R. F. L. Vermeulen, V. Newsum, K. K. L. Loh, J. C. de Sterke, W. J. Vlothuizen, R. N. Schouten, Carmen G. Almudéver, Leonardo DiCarlo, Koen Bertels
HPCA6
2019 Quantum Accelerated Computer Architectures
abstract
Modern computer applications usually consist of a variety of components that often require quite different computational co-processors. Some examples of such co-processors are TPUs, GPUs or FPGAs. A more recent and promising technology that is being investigated is quantum co-processors. In this paper, we present a modern computer architecture where a quantum co-processor is included as an additional accelerator. In such an environment, the idea is to execute the application on a heterogeneous architecture where the classic processor will execute the host part, but certain components will be mapped, in our case, on the quantum accelerator. To this purpose, we define the distinct layers for the quantum computer architecture where there is a clear boundary between the host program and quantum kernel(s). We also discuss the opportunities and challenges of mapping hybrid algorithms to such a heterogeneous quantum computer architecture.
Leon Riesebos, Xiang Fu 0003, A. A. Moueddenne, Lingling Lao, Savvas Varsamopoulos, Imran Ashraf 0002, Hans van Someren 0001, Nader Khammassi, Carmen G. Almudéver, Koen Bertels
ISCAS8
2018 Memory and Communication Profiling for Accelerator-Based Platforms
abstract
The growing demand of processing power is being satisfied mainly by an increase in the number of homogeneous and heterogeneous computing cores in a system. Efficient utilization of these architectures demands analysis of memory-access behaviour of applications and perform data-communication aware mapping of applications on these architectures. Appropriate tools are required to highlight memory-access patterns and provide detailed intra- application data-communication information to assist developers in porting existing sequential applications efficiently to these architectures. In this work, we present the design of an open-source tool which provides such a detailed profile for C/C++ applications. In contrast to prior work, our tool not only reports detailed information, but also generates this information with manageable overheads for realistic workloads. Comparison with the state- of-the-art shows that the proposed profiler has, on the average, an order of magnitude less overhead as compared to the state-of-the-art data-communication profilers for a wide range of benchmarks. The experimental results show that our proposed tool generated profiling information for image processing applications which assisted in achieving a speed-up of$6.14\times$and$2.75\times$for heterogeneous multi-core platforms containing an FPGA and a GPU as accelerators, respectively.
Imran Ashraf 0002, Nader Khammassi, Mottaqiallah Taouil, Koen Bertels
IEEE Trans. Computers2
2017 The engineering challenges in quantum computing
abstract
Quantum computers may revolutionize the field of computation by solving some complex problems that are intractable even for the most powerful current supercomputers. This paper first introduces the basic concepts of quantum computing and describes what the required layers are for building a quantum system. Thereafter, it discusses the different engineering challenges when building a quantum computer ranging from the core qubit technology, the control electronics, to the microarchitecture for the execution of quantum circuits and efficient quantum error correction. We conclude by discussing some compiler and programming issues relative to quantum algorithms.
Carmen G. Almudéver, Lingling Lao, Xiang Fu 0003, Nader Khammassi, Imran Ashraf 0002, Dan Iorga, Savvas Varsamopoulos, Christopher Eichler, Andreas Wallraff, Lotte Geck, Andre Kruth, Joachim Knoch, Hendrik Bluhm, Koen Bertels
DATE4
2017 QX: A high-performance quantum computer simulation platform
abstract
Quantum computing is rapidly evolving especially after the discovery of several efficient quantum algorithms solving intractable classical problems such as Shor's factoring algorithm. However the realization of a large-scale physical quantum computer is very challenging and the number of qubits that are currently under development is still very low, namely less than 15. In the absence of large size platforms, quantum computer simulation is critical for developing and testing quantum algorithms and investigating the different challenges facing the design of quantum computer hardware. What makes quantum computer simulation on classical computers particularly challenging are the memory and computational resource requirements. In this paper, we introduce a universal quantum computer simulator, called QX, that takes as input a specially designed quantum assembly language, called QASM, and provides, through agressive optimisations, high simulation speeds and large number of qubits. QX allows the simulation of up to 34 fully entangled qubits on a single node using less than 270 GB of memory. Our experiments using different quantum algorithms show that QX achieves significant simulation speedup over similar state-of-the-art simulation environment.
Nader Khammassi, Imran Ashraf 0002, Xiang Fu 0003, Carmen G. Almudéver, Koen Bertels
DATE1
2017 An experimental microarchitecture for a superconducting quantum processor
abstract
Quantum computers promise to solve certain problems that are intractable for classical computers, such as factoring large numbers and simulating quantum systems. To date, research in quantum computer engineering has focused primarily at opposite ends of the required system stack: devising high-level programming languages and compilers to describe and optimize quantum algorithms, and building reliable low-level quantum hardware. Relatively little attention has been given to using the compiler output to fully control the operations on experimental quantum processors. Bridging this gap, we propose and build a prototype of a flexible control microarchitecture supporting quantum-classical mixed code for a superconducting quantum processor. The microarchitecture is based on three core elements: (i) a codeword-based event control scheme, (ii) queue-based precise event timing control, and (iii) a flexible multilevel instruction decoding mechanism for control. We design a set of quantum microinstructions that allows flexible control of quantum operations with precise timing. We demonstrate the microarchitecture and microinstruction set by performing a standard gate-characterization experiment on a transmon qubit.
Xiang Fu 0003, M. Adriaan Rol, Cornelis Christiaan Bultink, Hans van Someren 0001, Nader Khammassi, Imran Ashraf 0002, R. F. L. Vermeulen, J. C. de Sterke, W. J. Vlothuizen, R. N. Schouten, Carmen G. Almudéver, Leonardo DiCarlo, Koen Bertels
MICRO5