Network-on-chip (NoC) has emerged as a vital factor that determines the performance and power consumption of many-core systems. This paper proposes a hybrid scheme for NoCs, which aims at obtaining low latency and low power consumption. In the presented hybrid scheme, a novel switching mechanism, called virtual circuit switching, is proposed to intermingle with circuit switching and packet switching. Flits traveling in virtual circuit switching can traverse the router with only one stage. In addition, multiple virtual circuit-switched (VCS) connections are allowed to share a common physical channel. Moreover, a path allocation algorithm is proposed in this paper to determine VCS connections and circuit-switched connections on a mesh-connected NoC, such that both communication latency and power are optimized. A set of synthetic and real traffic workloads are exploited to evaluate the effectiveness of the proposed hybrid scheme. The experimental results show that our proposed hybrid scheme can efficiently reduce the communication latency and power. For instance, for real traffic workloads, an average of 20.3% latency reduction and 33.2% power saving can be obtained when compared with the baseline NoC. Moreover, when compared with the NoC with virtual point-to-point connections (VIP), the proposed hybrid scheme can reduce the latency by 6.8% with the power decreasing by 11.3% averagely.

Stream architectures have emerged as a mainstream solution for computation-intensive applications due to their rich arithmetic units. This paper proposes a multithreading technique based on a scheduling scheme of stream programs on clustered VLIW stream architecture, which aims at optimal arithmetic unit utilization without increasing energy consumption. Its principle is to exploit more kernel-level parallelism for further optimal compilation by constructing homogeneous multiple threads on stream programs. Three phases are proposed in the scheduling scheme. First, threads in stream programs are replicated for constructing homogeneous multiple threads. Second, time step assignment for homogeneous multithreaded stream programs is utilized to obtain efficient kernel combination. Third, stream segmentation is presented to optimize both memory transfers and startup overheads of kernels. A set of benchmarks are exploited to evaluate the effectiveness of the proposed technique. Experimental results show that, with exploiting kernel-level software pipeline, the proposed technique improves the performance by 20.9 percent averagely with the energy decreasing by 7.6 percent. Utilizations of adders and multipliers are up to average 77.4 and 75.8 percent, increasing 17.0 and 13.3 percent, respectively. Moreover, the proposed technique performs an average of 12.5 percent improvement over CSMT4 with the energy decreasing by 12.0 percent.