The hardware implementation of nonlinear activation functions (AFs), such as the Sigmoid and Hyperbolic Tangent (Tanh), presents a significant bottleneck for deploying Recurrent Neural Networks (RNNs) on resource-constrained edge devices. Field Programmable Gate Arrays (FPGAs), as a leading platform for edge AI, face challenges in efficiently executing these functions due to their complex mathematical nature and limited computational resources. This paper proposes a novel, hardware-friendly piecewise linear (PWL) approximation method for implementing Sigmoid and Tanh functions. Our approach introduces new mathematical formulations for computing the y-intercept that significantly reduce Mean Squared Error (MSE) and Maximum Absolute Error (MXE) at no additional hardware cost. By consolidating the features of recent works, the proposed architecture eliminates a costly segment address encoder, supports pipelining for low-latency and high-frequency operation, and avoids the complexity and low precision of other methods. Moreover, it offers high configurability in bit width, number of segments, and input ranges, enabling adaptable deployment across diverse hardware and precision targets. A unified architecture is presented for both AFs, maintaining identical FPGA resource usage across functions. Experimental results demonstrate that the proposed method outperforms prior state-of-the-art designs by up to 18.52× in accuracy, 437.29× in latency, and 3.71× in frequency, and achieves LUT and flip-flop savings of up to 11.63× and 12.42×, respectively.

Quantum algorithms present unique advantages over classical methods but remain constrained by the limited number of qubits in current quantum computers.This limitation hinders their effectiveness in machine learning tasks, such as image classification.Despite its relevance, the impact of these constraints on quantum machine learning remains underexplored.This study addresses this gap by analyzing preprocessing techniques for preparing images on quantum processors.We evaluated 10 dimensionality reduction methods across four standard datasets using three distinct quantum neural network architectures.The results provide valuable insights into optimizing classification efficiency under qubit constraints, paving the way for broader applications of quantum machine learning.

The number of connected embedded edge computing Internet of Things (IoT) devices has been increasing over the years, contributing to the significant growth of available data in different scenarios. Thereby, machine learning algorithms arise to enable task automation and process optimization based on those data. However, due to some learning methods' computational complexity implementing geometric classifiers, it is a challenge to map these on embedded systems or devices with limited resources in size, processing, memory, and power, to accomplish the desired requirements. This hampers the applicability of these methods to complex industrial embedded edge applications. This work evaluates strategies to reduce classifiers' implementation costs based on the CHIP-clas model, independent of hyperparameter tuning and optimization algorithms. The proposal aims to evaluate the tradeoff between numerical precision and model performance and analyze the hardware implementations of a distance-based classifier. Two 16 -b floating-point formats were compared to the 32 -b floating-point precision implementation. Also, a new hardware architecture was developed and then compared to the state-of-the-art reference. The results indicate that the model is robust to low precision computation, providing statistically equivalent results compared to the baseline model, also pointing out statistically equivalent performance and a global speed-up factor of approx 4.39 in processing time.

Recent works have been claiming efficient hardware architectures, showing a considerable endeavor to implement chaotic maps in the digital domain. However, there is a critical issue with the chaotic degradation in the digital environment due to its finite numeric precision, that it is still an unsettled topic in the research community. Additionally, less attention has been given to synthesize a methodological approach to how to calculate the exponential function in hardware. In this paper, two novel hardware designs to represent the exponential chaotic map have been suggested. We have employed a perturbation method to avoid the chaotic degradation. 64-bit fixed-point and 32-bit floating-point formats were investigated. Moreover, an approximation of Euler's number by a finite series and the Horner's method have been undertaken to further minimize the proposed hardware. Results show that both proposed hardware architectures consume a fewer number of components. The designed systems present a positive Lyapunov exponent, which suggests a chaotic behavior. Ultimately, the NIST SP 800-22 test, the histogram, and the autocorrelation function show that the new hardware architectures present pseudo-random properties.

It is well known that there is an increasing interest in edge computing to reduce the distance between cloud and end devices, especially for machine learning (ML) methods. However, when related to latency-sensitive applications, little work can be found in ML literature on suitable embedded systems implementations. This article presents new ways to implement the decision rule of a large margin classifier based on Gabriel graphs as well as an efficient implementation of this on an embedded system. The proposed approach uses the nearest neighbor method as the decision rule, and the implementation starts from an RTL pipeline architecture developed for binary large margin classifiers and proposes the integration in a hardware/software co-design. Results showed that the proposed approach was statistically similar to the classifier and had a speedup factor of up to eight times compared to the classifier executed in software, with performance suitable for ML latency-sensitive applications.