In light of the increased concern about environmen-tal sustainability and the urgent need to reduce greenhouse gas emissions, methane (CH4) detection plays a critical role regarding air quality and climate change. As the major component of natural gas, methane significantly contributes to global warming and serves as an ancestor to the creation of harmful atmospheric pollutants. Therefore, effective detection and mitigation of methane leaks are essential for promoting sustainable practices. The first step to achieve this relies on the creation of systems capable of reliably and rapidly detecting methane leaks into the environment. This paper explores solutions for methane detection leaks in IoT natural gas monitoring systems, with a focus on the integration of low-power sensors, particularly using Metal-Oxide-Semiconductor (MOS) technology. The research encompasses various aspects, including the development of a test plan, to ensure validation of sensor performance across diverse scenarios, aiming to simulate sensor behaviour under conditions closely resembling the environments in which they will be deployed.

The increasing aim to use Machine Learning (ML) models to solve many problems targets now the end-devices. Implementing such models in Resource-Scarce Embedded Systems (RSES) improves battery life, privacy, and security. However, due to the lack of resources, the end-devices have called for tools to translate ML models built using Cloud computers to low-level languages with distinct degrees of optimizations. The following paper presents a Transpiler tool to translate trained Machine Learning models to plain C. The tool provides the transpiling of many ML algorithms, pre-processing algorithms, and decomposition models. As the paper shows, compared to other transpiling tools available on the market, CLARA provides the highest number of models to transpile and a multitude of optimization that targets memory and/or processing footprint.

Nowadays, and more than a decade after the first steps towards autonomous driving, we keep heading to achieve fully autonomous vehicles on our roads, with LiDAR sensors being a key instrument for the success of this technology. Such advances trigger the emergence of new players in the automotive industry, and along with car manufacturers, this sector represents a multibillion-dollar market where everyone wants to take a share. To understand recent advances and technologies behind LiDAR, this article presents a survey on LiDAR sensors for the automotive industry. With this work, we show the measurement principles and imaging techniques currently being used, going through a review of commercial systems and development solutions available in the market today. Furthermore, we highlight the current and future challenges, providing insights on how both research and industry can step towards better LiDAR solutions.

As the number of connected "things" increases at a very fast pace, the Internet of Things (IoT) ecosystem expands and nowadays covers a vast number of application domains, providing a large portfolio of solutions that are based on an evolving system, from the physical sensors (end devices) to the Cloud. When designing battery-powered end devices, previous research has identified several challenges such as wireless connectivity, battery lifetime, embedded intelligence, security and privacy concerns, and costs (modem unit, communication link and maintenance, among others). This paper focuses on the design and development of battery-powered IoT devices in which NarrowBand Internet of Things (NB-IoT) is used to provide seamless wireless connection, reduce power consumption, enhance communication coverage and minimize maintenance costs. The paper describes a typical use case where an Arm®Cortex®-M0+ and its low-power modes are exploited in order to design a low-power end device. Two different approaches, bare-metal and freeRTOS, for implementing the end device firmware are compared. Additionally, performance tests prove that increasing the clock frequency of the processor does not bring any advantage to this kind of applications.

Computer Vision is an emerging field with diverse applications which encompasses many algorithms with heavy computations. Histogram of Oriented Gradients-Support Vector Machine (HOG-SVM) is one such versatile algorithm used for object detection and image classification despite it's heavy computation load. Processing such an algorithm in real time with adequate throughput is a challenging task for a general purpose processor. Moreover, an embedded CPU with very limited processing power could least cater such heavy processing. Therefore our research in general focuses on developing application specific architectures for hardware acceleration of computer vision algorithms. This paper presents a continuation of a series of research to hardware accelerate HOG-SVM algorithm on FPGA. In this paper we mainly present the high performance application specific architecture for hardware acceleration of HOG-SVM which was successful in achieving a high throughput of 240fps on HD frames of size 1920x1080 which is a significant improvement of performance compared to previous research. On the other-hand, both hardware utilization and power consumption are minimized. A mechanism based around Block RAM (BRAM) structures and deep pipelining are used as the key architectural techniques of achieving high performance. The proposed design was deployed on Zynq 7000 FPGA platform which contains a hardwired ARM CPU along with the programmable FPGA fabric. The accelerator is deployed on the FPGA and integrated with the ARM CPU using AXI memory interfaces. A hardware thread model and bare-metal device drivers were developed which encapsulate the behavior of the accelerator as a hardware thread to the applications running on the ARM CPU.

The Internet of Things (IoT) is enabling the connection of an infinity of physical objects to the Internet through the wide deployment of low-end embedded devices at the network edge. However, providing communication capabilities to such devices, which allows them to connect to the Internet seamlessly, is not straightforward. Such features require the adoption of a lightweight and standard network stack, commonly integrated with an embedded operating system (OS), mitigating the complexity of developing resource-constrained wireless nodes. To assist in such tasks, some existing motes explore reconfigurable technology to accelerate compute-intense tasks (application- or network-related) in dedicated hardware accelerators. This article describes the deployment of a real-time OS, RIOT, on a reconfigurable end-device architecture for IoT, the CUTE Mote. The CUTE mote is based on a heterogeneous solution that combines a hard-core microcontroller unit beside reconfigurable technology and an IEEE 802.15.4-compliant radio transceiver.

Toxic products have been linked with some diseases, therefore, it is important to reduce the contact and ingestion of them by the human being. One place where is common to find trace elements of toxic products is in the food we eat every day. This happens, because those products are necessary to protect crops, specially from pest of fields. Losses in crops, due to pests of fields, are very common and unpredictable. Furthermore, pests tend to spread in short periods of time, and consume large areas of production, leaving nothing behind. Early pest detection has high importance. The following document presents the project called Intelligent Insect Monitoring System (I2MS). This project aims to early detect pests of fields using a system to attract insects by creating several stimuli (chromatic, food, sexual, and UV light). Next, the I2MS takes a picture of the insect and uses Cloud Based Machine Learning (ML) algorithms to classify the image, then checks if the insect is dangerous to the crops or not. The results showed the system's elements to be effective, making it possible to create a final prototype to be implemented in real-life situations in order to capture, identify, and alarm the farmers of possible pests.

Approaches to Dynamic Binary Translation (DBT) on resource-constrained embedded systems are not straight forward, leading to several improvements and acceleration suggestions that rely on dedicated hardware. Software to hardware of-floading is a common acceleration procedure used when software-only approaches do not meet the performance requirements, making such approach suitable to be successfully applied to DBT. This article approaches hardware offloading to address some limitations of an in-house DBT engine, the DBTOR, regarding its Translation Cache (TCache) management mechanism. The suggested approaches are non-intrusive to the target architecture, which cope with the commercial-off-the-shelf (COTS)-driven deployment of DBT for the resource-constrained embedded devices. This work proposes a TCache management hardware module that overpasses the linked list and hash table software-only approaches, resulting in a performance improvement of 25% and 26%, respectively.

The Internet of Things (IoT) is revolutionizing the Internet of the future and the way smart devices, people, and processes interact with each other. Challenges in endpoint devices (EDs) communication are due not only to the security and privacy-related requirements but also due to the ever-growing amount of data transferred over the network that needs to be handled, which can considerably reduce the system availability to perform other tasks. This paper presents an IPv6 over low power wireless personal area networks (6LoWPAN) accelerator for the IP-based IoT networks, which is able to process and filter IPv6 packets received by an IEEE 802.15.4 radio transceiver without interrupting the microcontroller. It offers nearly 13.24% of performance overhead reduction for the packet processing and the address filtering tasks, while guaranteeing full system availability when unwanted packets are received and discarded. The contribution is meant to be deployed on heterogeneous EDs at the network edge, which include on the same architecture, field-programmable gate array (FPGA) technology beside a microcontroller and an IEEE 802.15.4-compliant radio transceiver. Performed evaluations include the low FPGA hardware resources utilization and the energy consumption analysis when the processing and accepting/rejection of a received packet is performed by the 6LoWPAN accelerator.

Virtualization technology starts becoming more and more widespread in the embedded systems arena, driven by the upward trend for integrating multiple environments into the same hardware platform. The penalties incurred by standard software-based virtualization, altogether with the strict timing requirements imposed by real-time virtualization are pushing research towards hardware-assisted solutions. Among existing commercial off-the-shelf (COTS) technologies, ARM TrustZone promises to be a game-changer for virtualization, despite of this technology still being seen with a lot of obscurity and scepticism. In this paper we present a Lightweight TrustZone-assisted Hypervisor (LTZVisor) as a tool to understand, evaluate and discuss the benefits and limitations of using TrustZone hardware to assist virtualization. We demonstrate how TrustZone can be adequately exploited for meeting the real-time needs, while presenting a low performance cost on running unmodified rich operating systems. While ARM continues to spread TrustZone technology from the applications processors to the smallest of microcontrollers, it is undeniable that this technology is gaining an increasing relevance. Our intent is to encourage research and drive the next generation of TrustZone-assisted virtualization solutions.

This study presents an assessment of the OPC Unified Architecture as an integration framework for heterogeneous healthcare systems enabling compliance with the Industry 4.0 paradigm. The contributions of this work are: 1) a conceptual architecture with heterogeneous networks for enabling Internet of Things healthcare applications, 2) OPC UA data models based on the HL7 Reference Information Model for information exchange and storage, and 3) an analysis of how OPC UA can enable the healthcare sector to be part of the Industry 4.0.

With the increased complexity of low-end devices in the Internet of Things (IoT), mainly due to the connectivity and interoperability requirements, the development and configuration of embedded operating systems (OSes) for such devices is not straight forward. The complexity of the communication requirements is usually mitigated by the OS, e.g., the Contiki-OS, as it already incorporates an IoT-compliant network stack. Yet, the configuration of such stack requires major knowledge on the code structure, leading to additional development time, particularly when the network comprises several wireless nodes and individual configurations with subsequent firmware that needs to be generated. Based on a developed software modeling domain-specific language, this paper presents the EL4IoT framework. It aims to reduce and ease the development time by promoting a design automation tool that can configure, and automatically generate code (ready to compile) for low-end IoT devices running the Contiki-OS. Although leveraging the whole Contiki-OS modeling, this work only refactored and modeled the network stack while approaching the OS itself as one big building block or component. The proposed approach can be extended to other IoT-enabled OSes as well as integrated in other design automation tools.

Virtualization technology is well established in the server and desktop spaces, and has been spreading across embedded system market. This technology allows for the coexistence and execution of multiples operating systems on top of the same hardware platform, with proven technological and economic benefits. Hardware extensions for easing virtualization have been added into several commercial off-the-shelf processors. Among existing technologies, ARM TrustZone is gaining particular attention due to its broadly availability into ARM processors. However, existent TrustZone-assisted virtualization solutions are limited to a dual-guest and single-core configuration, which can lead to the starvation of the non-secure side when the secure world does not yield the processor. This work presents the extension of a TrustZone-assisted hypervisor to an asymmetric multi-processing configuration. We describe and demonstrate how to run a general-purpose operating system side-by-side with an real-time operating system in a Xilinx Zynq-based platform, enhanced with a dual ARM Cortex-A9. The achieved results demonstrate that the implemented multicore approach not only completely eliminates starvation, but also increases the general-purpose operating system's performance, especially when the real-time workload is demanding.

In the near future, billions of new smart devices will connect the big network of the Internet of Things, playing an important key role in our daily life. Allowing IPv6 on the low-power resource constrained devices will lead research to focus on novel approaches that aim to improve the efficiency, security and performance of the 6LoWPAN adaptation layer. This work in progress paper proposes a hardware-based Network Packet Filtering (NPF) and an IPv6 Link-local address calculator which is able to filter the received IPv6 packets, offering nearly 18% overhead reduction. The goal is to obtain a System-on-Chip implementation that can be deployed in future IEEE 802.15.4 radio modules.

Most hypervisors today rely either on (1) full virtualization on high-end hardware (i.e., hardware with virtualization extensions), (2) paravirtualization, or (3) both. These, however, do not fulfill embedded systems' requirements, or require legacy software to be modified. Full virtualization on low-end hardware (i.e., hardware without virtualization extensions), on the other end, has none of those disadvantages. However, it is often claimed that it is not feasible due to an unacceptably high virtualization overhead. We were, nevertheless, unable to find real-world quantitative results supporting those claims.

With the growing ubiquity of Internet of Things (IoT), myriads of smart devices connect and share important information over the Internet. In order to provide connectivity and interoperability of all the existing heterogeneous wireless devices, a full communication stack is proposed by the IoT Architecture Reference Model (IoT-ARM). From the sensor to the cloud, the proposed stack can be implemented on all IoT devices avoiding the battle for the wireless standard that will be adopted. This work in progress paper proposes an FPGA-based edge device for IoT, which uses SoC (System-on-Chip) FPGA technology to offload critical features of the communication stack to dedicated hardware, aiming to increase systems performance.

The pervasive use of embedded computing systems in modern societies altogether with the industry trend towards consolidating workloads, openness and interconnectedness, have raised security, safety, and real-time concerns. Virtualization has been used as an enabler for safety and security, but research works have proven that it must be extended and improved with hardware-based security foundations. ARM Trustzone has been used for the realization of Trusted Environments, however in this case real-time requirements are completely disregarded. This work in progress paper presents FreeTEE, an embedded architecture that emphasizes and preserves the real-time properties of the system but still guarantees security from the outset. TrustZone technology is exploited to implement the basic building blocks of a Trusted Execution Environment (TEE) as a lower-priority thread of a RTOS. Preliminary results demonstrated that the real-time properties of the RTOS remain practically intact.

Virtualization has been used as the de facto technology to allow multiple operating systems (virtual machines) to run on top of the same hardware platform. In the embedded systems domain, virtualization research has focused on the coexistence of real-time requirements with non-real-time characteristics. However, existent standard software-based virtualization solutions have been shown to negatively impact the overall system, especially in performance, memory footprint and determinism. This work in progress paper presents the implementation of an embedded virtualization architecture through commodity hardware. ARM TrustZone technology is exploited to implement a lightweight virtualization solution with low overhead and high determinism, corroborated by promising preliminary results. Research roadmap is also pointed and discussed.

The usage and deployment of Wireless Sensor Networks (WSN) is rapidly increasing in many different monitoring and control applications. In the majority of these applications, energy is a key factor in sensor networks since the sensor nodes are battery powered and hence have limited resources of energy. In this context, choosing a proper energy-efficient routing technique can increase the network life time. In this paper, a new Hybrid Energy-Efficient (HEE) routing protocol is proposed. HEE uses Direct Transmission (DT) and Minimum Energy Transmission (MTE) which are two of the simplest methods in terms of computational complexity. However the design of routing techniques is highly dependent on the application and the performance may vary based on environmental parameters. The novel proposed method is applicable for different networks regardless of the size and distances between the nodes and also with different parameters such as number of nodes and message length. Simulation results show how HEE performs more efficiently in terms of energy consumption when comparing to DT and MTE.

Wireless Sensor Networks are an emerging technology which has been recently adopted in many applications. Due to its wireless nature, the analysis of the radio propagation models plays an important role for performance evaluation in both theoretical and practical aspects. In this regards, path loss exponent is one of the most important parameter which has been considered widely in wireless communications analysis. There are several theoretical evaluations of path loss exponent for wireless sensor networks available in the literature. However there is a lack of experimental evaluation of both path loss exponent and the effect of shadowing. In this paper, three environments (free space, in building and industrial), where wireless sensor nodes are widely deployed, have been chosen in order to evaluate the experimental analysis. Path loss and path loss exponent are measured by means of Received Signal Strength Indicator (RSSI) and based on them, the standard deviation of shadowing effect is also calculated. All the measured parameters are compared with the theoretical analysis available in the literatures.

This paper describes an agile model-driven generative software development paradigm supported by mainstream tools to offer a significant leverage in hiding commonalities and configuring variabilities across families of video surveillance products while maintaining the new product quality. The integration of Agile and SPL (Software Product Line) paradigms is promoted to develop video surveillance systems as a pay-as-you-go fashion rather than developing an ex-nihilo new product, despite the perceived incompatibilities of these paradigms and potential challenges of such integration.

The development and maintenance of hardware/software Systems with a high level of variability is a complex task. At IVV Automacão, LDA the video surveillance system is implemented as a software product line that exploit the common component features that compose the video surveillance system family of products. In order to manage the system variability at code level, the IVV developers use C++ template metaprogramming (TMP). Although, TMP presents advantages in variability code management at compile time, the syntax and idioms of TMP are esoteric compared to conventional C++ programming, and TMP can be difficult to understand. In this paper we propose a novel approach to implement and maintain TMP code using a model-driven tool, that employs Template Markup Language with a XSLT transformer to automatic generate and maintain TMP code.

The proliferation of highly-configurable FPGA technology has allowed the implementation of dedicated systems of diverse configurations and fueled the software to hardware migration paradigm. This work demonstrates how the hardware implementation of virtualization technology affects the system reliability at several levels of abstraction. By correlating faults between the physical and virtual, the reliability impact of hardware-assisted virtualization is shown, as well as how runtime faults are capable of breaching virtualization. ISA profiling is used to assess reliability at early design stages and how its use can serve as a robustness guideline for hardware and software designers is explained.

This paper presents an innovative Multi Processor System on Chip (MPSoC) architecture based on Service Oriented Architecture (SOA) concepts. The proposed architecture promotes the design flexibility and interoperability by setting an implementation agnostic services' integration interface and being reconfiguration aware by design. The concept is tried with an example of an embedded legacy support system, a Dynamic Binary Translation (DBT) engine based on three services. DBT can solve the x86 architecture virtualization limitations. A SOA based MPSoC endowed of autonomous dynamic reconfiguration capabilities is introduced and pointed as a research opportunity. The introduction in the architecture of a Service Module responsible for Partial Runtime Reconfiguration (PRTR) is expected to dynamically adjust the architecture to better match the workload.

This paper presents a novel hypervisor engineered for aerospace applications using an object oriented approach embodying time and space partitioning (TSP) on a PowerPC core embedded in a FPGA, for the NetworkCentric core avionics [1] - an architecture of cooperating components and managed by a real-time operating system to implement dependable computing and targeting simplicity. To support partitioned IMA [2]software architectures our hypervisor adapted to the aerospace application domain the Popek and Goldberg's [3] fidelity, efficiency and resource control virtualization requirements by extending them with additional ones like timing determinism, reactivity and improved dependability. A distinctive feature of the hypervisor is its I/O device virtualization approach that guarantees real-time performance and small trusted computing base.

The heterogeneity of device interfaces and the disparity between interconnection standards leads to difficulty in achieving seamless device interoperability. The Open Services Gateway Initiative (OSGi) framework attempts to provide a unified Residential Service gateway by abstracting from the device interface and providing transparent methods for Service Oriented Architectures. However, it is not yet compliant with all standards and unsuited for some. This paper presents the development of a Multi-Camera Home Network System, using devices which implement three different protocols. The OSGi gateway bundles to handle the interoperability are described including one OSGi bundle for ONVIF devices. A Residential Service OSGi gateway is also presented and the difficulties faced with the integration of video streaming on the framework are presented, as well as the solutions used to tackle the problem.

This paper presents a novel segmentation approach for object detection in aquatic outdoor scenes such as swimming pools and its surroundings. This process is part of a video-based early drowning detection system for private swimming pools. Aquatic outdoor scenes are continuously changing due to reflections and refractions caused by water oscillation, severely affecting the results obtained by traditional segmentation schemes because water oscillation is perceived as motion detection of objects in the aquatic area. The novel segmentation technique is based in the separation of the special water environment and the rest of the scene, by means of an off-line automatically generated pool mask. The two areas are segmented with different algorithms, one for the aquatic scene and another for the surrounding area. Further, a two-step approach segmentation algorithm for the aquatic area was developed: the first segmentation step is based on the HSV invariant color model space; the second one consists in re-segmenting each region inside an expanded bounding box resulting from the first step. The second step increases segmentation quality up to 20%, as it captures parts of objects not detected before. The information extracted from the water surrounding area is also very important for object tracking and behaviour analysis purposes.

In this paper a real-time control system, developed to control a single-phase shunt active power filter used to minimize problems related to power quality in electrical systems is presented. The power stage of the active filter is based on a one-leg inverter, with two capacitors in the dc side, and a filter inductor in the ac side. The control system is based on the instantaneous power theory in the α-β-0 reference frame (pq-theory), modified to be applied in single-phase systems. In essence, the shunt active filter is designed to drain, from the electric grid, harmonic and reactive components of the load currents, such that the source current will become an almost sinusoidal waveform, with low harmonic distortion, and in phase with the system voltage. The control system is implemented using a development board (Atmel NGW100) and ensures simultaneous real-time acquisition of voltage and current data, the proposed system is capable of acquiring eight analog channels (16-bit resolution) simultaneously at 150ksps, based in the acquire data the power components calculation and compensation is performed accordingly to the p-q theory.