Analog to Digital Converters based on Voltage Controlled Oscillators are assumed very tolerant to sampling clock inaccuracies. This is due to the first-order shaping of sampling-induced errors, which appear indistinguishable from VCO phase quantization errors. A closer look to VCO-ADCs reveals that jitter errors can be problematic under different kinds of inputs and are affected by circuit impairments. This paper theoretically analyzes the behavior of pseudo differential VCO-ADCs in the presence of clock jitter and provides simulations of practical cases. In spite of being noise-shaped, the error induced by jitter is shown to depend on the input signal power. Afterwards, we analyze how VCO gain mismatch and offset among oscillators can affect clock jitter robustness. Also, in-band noise degradation due to out-of-band signal interferers is described.

A well established analysis technique of low-pass Sigma-Delta modulators is based on the white noise model, where quantization noise is assumed a uniformly distributed random signal. However, Sigma-Delta modulators exhibit numerous nonlinear effects that the white noise model fails to explain. Recently, a different way of describing low-pass Sigma-Delta modulators has been developed, establishing its similarities with VCO-based ADCs. A key idea in this new representation is the concept of the Pulse Frequency Modulation equivalent of a low-pass Sigma-Delta modulator. This paper reviews this new description with a simplified and intuitive approach and proposes new applications of the PFM analysis to other Sigma-Delta modulator architectures such as Band-Pass and Multistage modulators.

One of the limitations of conventional VCO-ADCs is the restriction to first-order noise shaping. True VCO-ADC architectures have been proposed to increase the noise-shaping order by cascading several VCO integrators, but without requiring analog feedback loops. A high noise-shaping order allows to reduce the input VCO frequency compared to a conventional VCO-ADC with similar dynamic range, which improves power consumption. Prior-art True VCO-ADC architectures represent state variables either with a unity-weighted code or with a single-bit. Unity-weighted encoding is a natural choice when ring oscillators are selected as loop filter integrators. However, chip area restrictions force unity-weighted state variables to have few levels. A reduced number of levels in the state variables limits the dynamic range of True VCO-ADCs. In this paper, we experimentally demonstrate a second-order audio VCO-based ADC that uses ring oscillators as integrators but employs Gray and binary encoded state variables. As a consequence, the complexity and area of the True VCO-ADC architecture is reduced, breaking the barrier that limits the dynamic range of prior designs. The proof-of-concept chip shows a dynamic range of 103 dB achieving a peak SNDR of 76.5 dB-A with a power of 250$\mu$W occupying 0.095$\text{mm}^2$in 130 nm CMOS.

Recently VCO-based filters have been used to implement feature extraction in voice recognition systems. Typically implemented filter structures embed the VCOs in a feedback loop. In these implementations, harmonic distortion has been observed in the output signal. This harmonic distortion has been attributed to ring oscillator nonlinearity but its origin stems from a system level problem. In this manuscript we will analyze this problem by looking at the cross modulation of Pulse Frequency Modulation (PFM) side-bands and we will explain how this creates the previously misunderstood harmonic distortion. Moreover, we will propose efficient techniques to mitigate these harmonic components and show that they can easily be implemented in hardware.

A ring-oscillator based circuit is proposed for features extraction tasks within smart speech recognition and voice activity detectors applications. The architecture performs all the operations needed for conventional features extraction but making use of only time-encoded based circuits in the analog domain. This results in a compact and simple structure, easily scalable and suitable for the deepest CMOS nodes leading for ultra-low and small solutions. The proposal is described theoretically and functionally checked with behavioral simulations in MATLAB. Additionally, the filtering stage is designed in a 65-nm process and validated with transient simulations providing promising results referring estimated power and area.

This work introduces a new VCO-ADC architecture. The power supply nodes of the inverters in a ring oscillator are sorted in two sets, and connected to two different input signals. We show in this paper that the oscillator frequency of such configuration reacts to the product of the two inputs. Therefore, the ring oscillator can be used both as a mixer and to digitally acquire the lowpass converted component. A first system-level approach is made to optimize the distortion by a proper number of taps in the ring oscillator. To confirm the system level predictions, some circuit simulations have been made. As a result, it is observed that VCO non-linearity limits the SNDR in a similar way as in conventional low pass VCOADCs. In a 65nm CMOS process, 55 dB of SNDR is achieved in a 5-MHz bandwidth for a 1 MHz downconverted signal, using a sampling clock of 2.5 GHz and input signals centered in 70 MHz and 71 MHz.

Digital sensors contain reconfigurable Sigma-Delta modulators that support different working modes. Depending on the timing of reconfiguration, high amplitude transients may appear at the sensor output. This article analyzes the transient response of discrete time Sigma-Delta modulators to find the optimal reconfiguration moment. It is shown that the transient is optimal when the first state variable of the loop filter is zero at the reprogramming instant. The optimal time is predicted with a pulse frequency modulator model. Finally, a set of general equations are given to predict the transient sequence for any modulator order and topology.

This paper presents a novel approach to analyze clock jitter influence in the performance of continuous-time sigma-delta modulators. The analysis is based on projecting all the signals and operations over an artificial time-base relative to the sampling clock, on which the sampling period can be considered constant. In the proposed time-base, clock jitter can be modeled as the modulation of the input signal frequency and the integrators gain. Unlike standard techniques, we do not rely on the feedback pulse properties, which enables a broader application of our technique to band-pass or VCO-based sigma-delta modulators. In this paper, we present the basic theory of this technique and its application to some practical examples, showing a good matching between prediction and numerical simulation.

The parallelism between a first-order sigma-delta modulator and a VCO-based ADC allows to calculate the DFT of the sigma delta sequence using Pulse Frequency Modulation theory. This paper exploits this parallelism to propose a more general model that links continuous time sigma delta modulators of an arbitrary order with Pulse Frequency Modulators. This novel point of view also predicts the spectral contents of a sigma delta encoded sequence beyond the white quantization noise model. The quantization noise can be split in two components, a deterministic one representing the carrier harmonic sidebands of a Pulse Frequency Encoded signal and a noise shaped pseudorandom signal representing the sampling operation. We seize these findings to propose a conjecture on the stability of a sigma delta modulator.