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David J. Allerton

dblp:120/6363 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 1989
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Software engineering, systems software and programming languages · 1Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 100%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › register file
multi-ported register file		 0.011989
A Three-Port/Three-Access Register File for Concurrent Processing and I/O Communication in a RISC-Like Graphics Engine · ISCA 1989
Processor architecture and microarchitecture
register file		 0.011989
A Three-Port/Three-Access Register File for Concurrent Processing and I/O Communication in a RISC-Like Graphics Engine · ISCA 1989

Methods — techniques the papers use, named apart from their topics

register file design · 0.0
YearPublicationVenuePosition
1989 A Three-Port/Three-Access Register File for Concurrent Processing and I/O Communication in a RISC-Like Graphics Engine
abstract
A novel method that provides extremely fast Input/Output (I/O) data transfer to a RISC-like graphics engine is presented. This method employs a combined two-port / two-access and a three-port / three-access register file used for concurrent processing and I/O data transfer. The three-port cell employed is only 25 % larger than the two-port cell, offering considerable advantages over alternative approaches, such as FIFOs or register banks.
Manuel Lois Anido, David J. Allerton, Ed Zaluska
 ISCA2
1988 The architecture of RIG: A RISC for image generation in a multi-microprocessor environment
Manuel Lois Anido, David J. Allerton, Ed Zaluska
 Microprocess. Microprogramming2
1987 Real-Time Scan-Line In-Fill
abstract
A novel algorithm is described to perform in-fill of wire-frame polygons, typically for application in visual systems for flight simulation. Post-processing is performed on an image formed in a conventional raster-scan framestore using edge-detection in scan-line order. A prototype real-time implementation of this algorithm is operational and is also presented.
David J. Allerton, J. D. Evemy, Ed Zaluska
 Eurographics1