This article consists only of a collection of slides from the author's conference presentation.

We present the design, implementation, and evaluation of CONGA, a network-based distributed congestion-aware load balancing mechanism for datacenters. CONGA exploits recent trends including the use of regular Clos topologies and overlays for network virtualization. It splits TCP flows into flowlets, estimates real-time congestion on fabric paths, and allocates flowlets to paths based on feedback from remote switches. This enables CONGA to efficiently balance load and seamlessly handle asymmetry, without requiring any TCP modifications. CONGA has been implemented in custom ASICs as part of a new datacenter fabric. In testbed experiments, CONGA has 5x better flow completion times than ECMP even with a single link failure and achieves 2-8x better throughput than MPTCP in Incast scenarios. Further, the Price of Anarchy for CONGA is provably small in Leaf-Spine topologies; hence CONGA is nearly as effective as a centralized scheduler while being able to react to congestion in microseconds. Our main thesis is that datacenter fabric load balancing is best done in the network, and requires global schemes such as CONGA to handle asymmetry.

Program behavior studies demonstrate that a significant fraction of load instructions in a program read the data stored by an instruction in the immediate past. In this paper, we propose a scheme entitled the Code Coalescing Unit that eliminates several of the memory access instructions by buffering the data in a Store Register Rename Buffer (SRRB) which is similar to the store buffer and renaming the instructions that use the data to access it directly from the buffer. The Code Coalescing Unit (CCU) can be considered as an extension to the fill unit proposed by S.W. Melvin et al. (1988). Their fill unit groups together micro-operations into larger atomic units and stores them into the decoded instruction cache (DIC) which are later executed directly from the DIC. The original fill unit grouped together micro-operations into larger atomic units, but the proposed Code Coalescing Unit goes further by eliminating particular load operations in the process of grouping together micro-operations. Experiments on eight applications including Microsoft Word for Windows, Microsoft C++ compiler and two SPEC programs demonstrate that approximately 25%, 34% or 42% of all load operations performed by these applications could have been eliminated using a Code Coalescing Unit in conjunction with a Store Register Rename Buffer of 8, 16 or 32 entries respectively.