The performance gap between in-order (InO) and out-of-order (OoO) cores comes from the ability to dynamically create highly optimized instruction issue schedules. In this work, we observe that a significant amount of performance benefit of OoO scheduling can also be attained by supplementing a traditional InO core with a small and speculative instruction scheduling window, namely SpecInO. SpecInO monitors a small set of instructions ahead of a conventional InO scheduling window, aiming at issuing ready instructions behind long-latency stalls. Simulation results show that SpecInO captures and issues 62% of dynamic instructions out of program order. To this end, we propose a CASINO core microarchitecture that dynamically and speculatively generates OoO schedules with near-InO complexity, using CAScaded IN-Order scheduling windows. A Speculative IQ (S-IQ) issues an instruction if it is ready, or otherwise passes it to the next IQ. At the last IQ, instructions are scheduled in program order along serial dependence chains. The net effect is OoO scheduling via collaboration between cascaded InO IQs. To support speculative execution with minimal cost overhead, we propose a novel register renaming technique that allocates free physical registers only to instructions issued from the S-IQ. The proposed core performs dynamic memory disambiguation via an on-commit value check by extending the store buffer already existing in an InO core. We further optimize energy efficiency by filtering out redundant associative searches performed by speculated loads. In our analysis, CASINO core improves performance by 51% over an InO core (within 10 percentage points of an OoO core), which results in 25% and 42% improvements in energy efficiency over InO and OoO cores, respectively.

This article proposes REACT, a regular expression matching accelerator, which can be embedded in a modern Solid-State Drive (SSD) and a novel data access scheduling algorithm for high matching throughput. Specifically, REACT, including our data access scheduling algorithm, increases the utilization of SSD and the degree of internal memory parallelism for pattern matching processes. While the low-level flash exhibits long latency, modern SSDs in practice achieve high I/O performance by utilizing the massive internal parallelism at the system-level. However, exploiting the parallelism is limited for pattern matching since the subblocks, which constitute an input data and can be placed in multiple flash pages, should be tested in a sequence to process the input correctly. This limitation can induce low utilization of the accelerator. To address this challenge, the proposed REACT simultaneously processes multiple input streams with a parallel processing architecture to maximize matching throughput by hiding the long and irregular latency. The scheduling algorithm finds a data stream which requires a sub-block in closest time and prioritizes the access request to reduce the data stall of REACT. REACT achieves maximum 22.6 percent of matching throughput improvement on a 16channel high-performance SSD compared to the accelerator without the proposed scheduling algorithm.

Coarse-grained instruction commit mechanisms enabled the effective size of the instruction window to be as large as possible by committing a group of instructions atomically. Within a group, the reorder buffer (ROB) and physical registerfile (PRF) entries are conservatively managed, and thus the instruction window can handle more in-flight instructions beyond the hardware limit. However, previous approaches have suffered from high storage requirements for managing group information and unbalanced lifetime of instruction window resources, i.e., the ROB and PRF. In this paper, we propose an OverCome microarchitecture based on a history-based approach to address these problems. First, OverCome retains the conservative allocation of the ROB regardless of the group size limit, thereby providing high scalability. Second, it handles the information of numerous groups with a low storage cost. These two techniques achieve a significant reduction in the pressure on the ROB; thus, a new bottleneck arises: the pressure on the PRF. To address this issue, we propose a novel register renaming technique to reduce the lifetime of physical registers to a large extent, by tightly coupling the early release and lazy allocation schemes. Thus, the proposed design strikes a balance between the ROB and PRF requirements. Detailed evaluation of the proposed techniques on a state-of-the-art superscalar processor shows that our proposals augment the effective size of the instruction window by more than 4×, with a net overhead of less than 3 percent of the core area.

In this paper, a new channel model is presented for molecular communications (MC), where a point source emitted by the transmitter undergoes three phases, with effect of convection dominating in the first two phases, whereas diffusion prevailing in the final phase. The point source obtains its initial velocity and passes through the nozzle of the nanomachine transmitter in the first phase, followed by a deceleration process in the second phase. The free diffusion model is considered in the third phase. Based on this channel model, the energy transfer issue for two-way MC system is also taken into account, in which one of the transceivers is assumed to have abundant information molecules from its ambient environment, whereas the other one obtains the information molecules by implementing the simultaneous molecular information and energy transfer (SMIET). Finally, analytical bit error rate (BER) expressions are validated by computer simulations. Our results suggest that the symbol duration and the SMIET order significantly influence the BER performance in our two-way MC system.

This paper proposes a microarchitectural mechanism to minimize the latency of thread migration for a tightly-coupled heterogeneous core, which has two execution backends (e.g., in-order and out-of-order execution pipelines). The proposed mechanism examines the dependencies between all in-flight instructions that reside in one of the backend pipelines, and allows both pipelines to simultaneously perform the instruction execution. At the microarchitectural level, instruction dispatching and instruction execution are seamlessly performed across thread migration, and therefore, this simultaneous backend execution can accelerate the program execution, which cannot be achieved with an existing migration mechanism. Accelerating thread migration will increase the overall performance with low power overhead, providing high energy efficiency. As compared to a baseline heterogeneous core with an existing migration mechanism, the simultaneous backend execution reduces 8.2 percent of the total execution cycle and consumes 2.9 percent lower total energy on average across SPEC CPU2006 benchmarks, which results in an improved energy efficiency of 10.9 percent in terms of the energy-delay product.

In diffusion-based molecular communication, information transport is governed by diffusion through a fluid medium. The achievable data rates for these channels are very low compared to the radio-based communication system, since diffusion can be a slow process. To improve the data rate, a novel multiple-input multiple-output (MIMO) design for molecular communication is proposed that utilizes multiple molecular emitters at the transmitter and multiple molecular detectors at the receiver (in RF communication these all correspond to antennas). Using particle-based simulators, the channel's impulse response is obtained and mathematically modeled. These models are then used to determine interlink interference (ILI) and intersymbol interference (ISI). It is assumed that when the receiver has incomplete information regarding the system and the channel state, low complexity symbol detection methods are preferred since the receiver is small and simple. Thus, four detection algorithms are proposed-adaptive thresholding, practical zero forcing with channel models excluding/including the ILI and ISI, and Genie-aided zero forcing. The proposed algorithms are evaluated extensively using numerical and analytical evaluations.

In molecular communication information is transferred with the use of molecules. Molecular multiple-input multiple- output (MIMO) system with drift (positive velocity) at macro- scale will be presented and the improvement against single- input single-output (SISO) molecular communication systems will be verified via our testbed. Until now it was unclear whether MIMO techniques, which are extensively used in modern radio frequency (RF) communications, could be applied to molecular communication. In the demonstration, using our MIMO testbed we will show that we can achieve nearly 1.7 times higher data rate than SISO molecular communication systems. Moreover, signal-to-inter-link-interfeence metric for one-shot signal will be depicted for a given symbol duration.

Two main problems prevent a parallel garbage collection (GC) scheme with lock-based synchronization from providing a high level of scalability: the load imbalance and the runtime overhead of thread synchronization operations. These problems become even more serious as the number of available threads increases. We propose the Mark-Sharing algorithm to improve the performance of parallel GC using transactional memory (TM) systems. The Mark-Sharing algorithm guarantees that all threads access the shared resource by using both the task-stealing and task-releasing mechanisms appropriately. In addition, we introduce a selection manager that minimizes the contention and idle time of garbage collectors by maintaining task information. The proposed algorithm outperforms the prior pool-sharing algorithm of GC in the HTM, providing more than 90% performance improvement on average.

Recently many researches have been studied to run autonomous flying vehicles. Especially, quadrotor VTOL (Vertical Take-Off and Landing) has been a challenging subject. To stabilize the quadrotor system, many control algorithms and sensor systems have been developed. Most of them are based on the sensors like accelerometer, gyroscope, or IMU (Inertial Measurement Unit) to measure the attitude of quadrotor. Instead of using these conventional sensors, we apply one vision sensor to stabilize the attitude of a quadrotor system. To achieve this, four laser diodes are evenly distributed in the bottom plane of quadrotor, and then they point downwards. The positions of projected laser markers depend on the attitude and height of the quadrotor. We develop a control algorithm to stabilize the attitude as well as to control the height of a quadrotor. We show that the visual tracking of the laser markers is sufficient to estimate the state of the quadrotor attitude and control the attitude into a desired state.