The design of large devices suggests fundamental and efficient innovation in the field programmable gate array (FPGA) interconnect structure to improve power consumption, density, and performance. Mesh-based FPGA architectures are generally designed to maximize logic utilization and to ensure layout scalability whereas tree-based FPGA architectures are designed to increase interconnect utilization. In this article, we propose a new mesh of trees (MoTs) FPGA architecture where we try to benefit from mesh of clusters (MoCs) FPGA layout scalability and tree-based FPGA efficient intracluster interconnect utilization, thanks to the butterfly fat-tree (BFT) topology. In order to attain the efficient use of the proposed routing interconnect resources, we develop computer-aided design (CAD) tools that respond to the target MoTs FPGA features. In addition, we define the power, area, and delay metric models according to the proposed architecture criteria. The experimentation results show that MoTs architecture with a cluster arity 32 offers the best tradeoff between power, area, and delay. Furthermore, we conduct a comparison between MoTs and MoCs FPGAs in general and the best MoTs and MoCs solutions, which ensure the best tradeoff between power, area, and delay in particular. The results show that the best MoTs architecture reduces power, area, delay, and energy by an average of 29%, 6%, 40%, and 47%, respectively, in comparison with the best MoCs architecture.

Computer-Aided Design (CAD) tools represent a major factor to enhance the quality of Field Programmable Gate Arrays (FPGAs) and use their architectural resources to their full potential. Since they can be developed to satisfy application constraints like surface, speed and energy while responding to Time-to-market requirements. In this paper, we explore the impact of T-VPack and First Choice (FC) clustering algorithms on the performance of Multilevel Switch Boxes (MS) FPGA with Long Wires (LWs). Indeed, the performance of an FPGA is highly sensitive to the mapping of Logic Blocks (LBs) on FPGA architecture. This work shows that FC ameliorates power consumption, area, critical path delay and energy compared to T-VPack.

In this paper, we propose a 2D and 3D interconnect network based on a Mesh-of-Clusters (MoC) topology for the implementation of an efficient Field Programmable Gate Arrays (FPGA) architecture. Proposed MoC-based FPGA architecture presents a new hierarchical Switch Box (SBs) and depopulated intra-cluster interconnect based on the Butterfly-Fat-Tree (BFT) topology. Long routing wires which span multiple SBs in every row and column were used in order to improve performance. By adjusting the percentage of long wire and span, we can design and build 3D high density MoC-based FPGA. To design 3D MoC-based FPGAs, we cut the 2D FPGA into two equal FPGA dies and we adjust the long wire span factor to connect the two dies. Then, these long wire segments are converted as 3D through silicon via (TSV). We present also a design methodology and CAD tools to explore the performance of proposed 2D and 3D MoC-based FPGA architectures in term of power, energy, area and delay. Experimental results with large benchmarks show that with 3D MoC-based FPGA the average gains in terms frequency, energy and area are 23%, 37% and 47% respectively, compared to 2D MoC-based FPGA.