This paper presents a dual-channel$\times 2$/$\times 3$broadband frequency multiplier based on a single core, capable of simultaneously realizing frequency doubling and tripling under single-band input. A modified Enz-Krummenacher-Vittoz (EKV) model combined with harmonic impedance analysis is employed to investigate both the concurrent generation of second and third harmonics and their mutual interaction. A multifunctional broadband output network is proposed to extract harmonics, provide impedance matching, and suppress unwanted frequency components. The frequency multiplier is implemented in 40 nm CMOS, occupying a core area of only 0.05 mm2. Measured results show a second harmonic output power of 2 dBm with a 3-dB bandwidth spanning 110–174 GHz, and a third harmonic output power of -3.8 dBm with a 3-dB bandwidth of 167–254 GHz, achieving a total bandwidth coverage exceeding 140 GHz. To the best of the authors’ knowledge, this work is the first non-injection-locked dual-channel frequency multiplier based on a single core in CMOS process. It also achieves the widest 3-dB bandwidth among CMOS or SiGe-based frequency doublers and triplers operating in the D-band and the 170–260GHz range.

This paper presents a 24-30 GHz sideband reuse transmitter with high image rejection ratio (IRR) and high local oscillator feedthrough (LOFT) suppression for 5G millimeter wave communication. Based on the Hartley heterodyne structure, the proposed sideband reuse scheme significantly reduces the required LO bandwidth for covering the 24–30 GHz RF output range. The LO bandwidth is narrowed to 2 GHz from the 6 GHz required in conventional heterodyne transmitters. As a result, excellent IRR and LOFT suppression are achieved across the operating band using a narrowband and simple-structure I/Q LO generation network. Moreover,$g_{\text {m}}$-boosting, linearity-enhanced mixer and power combining technique are employed in the transmitter to achieve high gain and output power. The proposed transmitter is fabricated in low-cost 180-nm bulk CMOS process. It delivers superior IRR greater than 37 dBc and LOFT below −41 dBc across the 24-30 GHz. The small signal 3-dB gain bandwidth spans from 24 to 30 GHz, with a peak gain of 21.7dB attained at 27.5 GHz. The complete transmitter achieves a measured saturated output power (Psat) of 16.5 dBm with 11.1% power-added efficiency (PAE) and the output 1-dB compression point (OP${}_{\mathbf {1dB}}$) of 14.8 dBm at 1.8V supply. Furthermore, with the 64-quadrature amplitude modulation (QAM) modulated signal, the proposed transmitter achieves an average output power of 8.7dBm at 27.5 GHz with the adjacent channel power ratio (ACPR) of −32.7 dBc.

This paper presents a compact gain-boosted up-conversion mixer integrated with input active balun in D-band. To simplify the driving stages of power amplifiers and enable large-scale integration in millimeter-wave systems, a proposed gain-boosted technique is introduced. This technique enhances the conversion gain of the mixer without increasing power consumption or footprint, achieved through the synergistic combination of negative resistance compensation (NRC) and current-reuse techniques. Furthermore, a wideband balance compensation technique is utilized at the local oscillator (LO) input, and an active balun is implemented at the intermediate frequency (IF) input, replacing the conventional large-area passive balun. These innovations lead to a more compact high-gain mixer design while achieving high-speed performance. For validation, the proposed up-conversion mixer is fabricated in a 40-nm CMOS. It boasts a total area of 0.15 mm2 ($0.033~\lambda ^{2}$), with a core area of 0.024 mm2 ($0.0052~\lambda ^{2}$). It achieves a measured conversion gain of 4.1 dB at 136 GHz. The measured saturation power is −5 dBm, with a data transmission rate of 42 Gbps, while consuming a power consumption of 10.8 mW only. To the best of our knowledge, this design achieves the highest conversion gain among D-band up-conversion mixers in CMOS technology and represents the smallest footprint among up-conversion mixers integrated with balun in D-band.

This work presents a compact integrated CMOS radiator with a tuning range of 321-343 GHz. The miniaturization and enhanced performance of the radiator is achieved through co-designing a ring oscillator and a multifunctional antenna. The multi-stage ring oscillator features a variable common-source (CS) stage, which is proposed to achieve a broad frequency tuning range. To enhance the performance of the proposed variable CS stage for terahertz (THz) oscillator, wideband load impedances for all harmonics are theoretically analyzed and recursively optimized. The multifunctional antenna integrates six key functions into a simple compact structure: 1) inherently embedding the ring oscillator within a symmetric layout to ensure uniform operation, 2) directly combining the desired third harmonic signals without bulky and lossy passive networks, 3) radiating the desired third harmonic, 4) suppressing unwanted even harmonics, 5) providing fundamental inductance for the ring oscillator, and 6) supplying DC bias at virtual ground. For experimental validation, a THz radiator including a four-stage ring oscillator and a multifunctional antenna, is co-designed and fabricated in 40 nm CMOS process. The total chip area is as compact as 0.12 mm${}^{\mathbf {2}}$. The measured output power and EIRP are −3.6 dBm and −9 dBm at 343 GHz, respectively, with a low DC power consumption of 46 mW. Moreover, the CMOS THz radiator is with a measured frequency tuning range of 6.7%, and DC-to-$P_{\mathbf {out}}$efficiency of 0.95%. This compact radiator demonstrates promising potential for wideband and high-efficiency THz applications.

For millimeter-wave (mmWave) integrated circuits, an on-chip calibration method with high accuracy is crucial. For accurate calibration, this paper proposes a thru-reflect-line neural network (TRL-NN), by incorporating machine learning techniques into the classical thru-reflect-line (TRL) calibration method. Compared with conventional TRL, the proposed TRL-NN demonstrates enhanced accuracy. The TRL-NN utilizes deep neural networks (DNNs) to predict$S$-parameters of the device under test (DUT). The proposed method also achieves high calibration accuracy even when non-standard calibrators are employed. For validation with comparison, 100 randomly generated DUTs are calibrated using both proposed TRL-NN and classical TRL methods. The proposed TRL-NN method is further experimentally demonstrated to accurately calibrate a transmission line covering the whole D-band of 110–170 GHz.

This manuscript introduces an integrated power amplifier (PA) meticulously designed for the D-band, addressing the interconnect challenges between power amplifiers and transmitting antennas operating in the millimeter-wave and terahertz frequency ranges. The proposed PA design is founded on a 2-way combined, low-loss balanced amplifier technology. The low-loss balanced amplifier technology utilizes a four-stage differential common-source amplifier unit, featuring the lossy over-neutralization technique as foundational building blocks. Simultaneously, the combining network integrates a quadrature coupler designed with a novel slow-wave coupled line. In contrast to conventional coupled line structures, the novel slow-wave coupled-line structure excels in low loss, high coupling coefficient, and the demand for high characteristic impedance while maintaining a high phase constant, contributing to a more compact form factor. Fabricated utilizing a 40-nm CMOS process, the amplifier showcases a total area of 0.34 mm2 ($0.074\lambda ^{2}$), with a core area of 0.11 mm2 ($0.024\lambda ^{2}$). At 130 GHz, it attains a peak gain of 23 dB, a saturated output power of 13.2 dBm. Moreover, the entire D-band exhibits outstanding matching characteristics. To the best of our knowledge, this is the first published CMOS balanced power amplifier designed in D-band.

Millimeter-wave (mm-Wave) and terahertz (THz) technologies are promising for many emerging applications including 6G communication. At such high frequencies, it is very challenging to accurately and efficiently integrate discrete passive circuits with tiny silicon chips. Therefore, it is meaningful to explore the feasibility of directly integrating passive circuits into silicon chips, to achieve mm-Wave and THz system-on-chip (SoC) with full integration, low interconnection loss and affordable cost. Driven by this goal for D-band (110–170 GHz) SoC, this paper presents two couplers in standard CMOS process, i.e., 180° rat-race and 90° branch-line couplers. To reduce the footprint, multilayered slow-wave unit cell is proposed to efficiently use back-end-of-lines (BEOLs) in standard silicon process. Compared with conventional microstrip line, the proposed unit cell increases the relative permittivity by 2.4 times, and achieves 44.2% length reduction at 140GHz. Both theoretically modeled and full-wave simulated results indicate that, the proposed multilayered unit cell features distinct slow-wave effect, to slow down the phase velocity of electromagnetic waves, and therefore reduce the size of two couplers to 0.038 mm2 and 0.04 mm2, respectively. To the best knowledge of the authors, this is the first time to use multilayered slow-wave unit cell for D-band CMOS couplers, which is a basic block of mm-Wave and THz transceiver chip.