This paper presents a 1 GHz low power Direct Digital Synthesizer (DDS) with sub-Hertz frequency resolution operating at 9.4 K. The proposed circuit is used as a signal generator for microwave (MW) driven qubit entanglement operations in trapped-ion quantum computers for improved gate fidelity. This is realized by utilizing the generated waveform as the carrier for the qubit’s driving signal. This signal is further frequency multiplied and envelope modulated to get the final qubit driving signal. The proposed mixed-signal-circuit operates at a 2.5 V/1.5 V analog and 1.5 V digital supply, 1 GHz input clock and consumes a total power of 27.64 mW. The frequency normalized-total power consumption, is only 27.64 µW/MHz. The DDS gives a worst case narrow band SFDR of 32.72 dB across the octave of frequencies to be synthesized. The design is manufactured in a 0.13 µm SiGe BiCMOS technology and has a core area of 0.69 mm2.

This work presents an ultra-low-power, single-ended successive approximation register (SAR) analog-to-digital converter (ADC) designed explicitly to digitize sensor data. Due to the single-ended nature of the sensor’s output data, very efficient designs for differential SAR ADCs cannot be utilized. Hence, a monotonic capacitor switching procedure for single-ended inputs has been developed and is introduced in this paper. Re-charging of capacitances during the SAR algorithm is no longer required, resulting in significant energy savings compared to conventional approaches.The SAR ADC is implemented in a 22nm CMOS FDSOI technology. It achieves a measured signal-to-noise and distortion ratio (SNDR) of 49.1dB and a spurious-free-dynamic-range (SFDR) of 61dB. It draws a simulated 1.2μW yielding a Walden figure of merit (FoMW) of 50.2fJ/conversion step at a sampling rate of 100kS/s. The circuit occupies an area excluding pads of only 275 x 220μm2.

This paper presents a new family of backpropagation-free neural architectures, Gated Linear Networks (GLNs). What distinguishes GLNs from contemporary neural networks is the distributed and local nature of their credit assignment mechanism; each neuron directly predicts the target, forgoing the ability to learn feature representations in favor of rapid online learning. Individual neurons are able to model nonlinear functions via the use of data-dependent gating in conjunction with online convex optimization. We show that this architecture gives rise to universal learning capabilities in the limit, with effective model capacity increasing as a function of network size in a manner comparable with deep ReLU networks. Furthermore, we demonstrate that the GLN learning mechanism possesses extraordinary resilience to catastrophic forgetting, performing almost on par to an MLP with dropout and Elastic Weight Consolidation on standard benchmarks.

This work presents a novel control loop concept to adjust dynamically a differential ring oscillators (DRO) biasing in order to improve the phase noise performance (PN) in the ultra-low-power domain. Applying this proposed feedback system on any DRO with a tail current source is possible. The following paper presents the proposed concept and includes measurements of a 180 nm CMOS integrated prototype system, which underlines the feasibility of the discussed idea. Measurements show an up to 35 dBc/Hz phase noise improvement with an active control loop. Moreover, the tuning range of the implemented ring oscillator is extended by about 430 % compared to fixed bias operation. These values are measured at a minimum oscillation power consumption of 55 pW/Hz.

This paper presents a wide-dynamic-range high-resolution time-domain converter concept tailored for low-power sensor interfaces. The unique system structure applies different techniques to reduce circuit complexity, power consumption, and noise sensitivity. A multi-cycle concept allows a virtual delay line extension and is applied to achieve high resolution down to 1ns. At the same time, it expands the dynamic range drastically up to 2.35 ms. Moreover, individually tunable delay elements in the range of 1ns to 12 ns allow on-demand flexible operation in a low- or high-resolution mode for smart sensing applications and flexible power control. The concept of this paper is evaluated by a custom-designed FPGA supported PCB. The presented concept is highly suitable for on-chip integration.