This article presents a boost converter based on a maximum power point tracking (MPPT) circuit, and a multicurrent detector (MCD), an offset cancellation circuit to achieve high efficiency over a wide range of input power. The proposed boost converter employs an MPPT design for adaptive on-time operation, which adjusts the on-time width to achieve maximum efficiency depending on the input voltage. In addition, a phase frequency detector-based offset cancellation method is proposed to minimize power loss by accurately sensing the current detector, thereby transferring power. Therefore, the proposed method achieves a significant efficiency improvement of up to 10 % by implementing high-precision offset cancellation with an offset level of approximately$5~\mu $A, which is significantly lower than the conventional MCD offset of over 60 mA of maximum offset current level. The proposed boost converter fabricated in a 130 nm Bipolar-CMOS-DMOS (BCD) process occupies an active area of 0.806 mm2 and can self-start with a minimum input voltage of 450 mV ($40~\mu $W) and achieve maximum efficiency of 92.7 %.

A compact power-on-reset (POR) circuit with a configurable brown-out reset (BOR) function is presented. An integrated voltage reference (VR) circuit provides a constant bias voltage that facilitates voltage-triggered POR/BOR operation, reliably preventing POR signal generation when the ramping supply voltage (${V} _{\text {DD}}$) level is too low. Moreover, the proposed POR circuit features a fast, configurable POR/BOR operation owing to an inverter-based trip point detector (TPD), which triggers the reset signal with a programmable trip point. The prototype POR circuit achieves a POR level higher than 752 mV with a maximum POR delay of$16.4~\mu $s at a 0.8–1.2-V${V} _{\text {DD}}$, supporting a wide range of supply ramping time from$1~\mu $s to 1 s. In addition, the prototype detects brown-out events with a supply drop of 0.1–0.4 V, generating the BOR signal. Designed using a 28-nm CMOS process, the prototype has a compact active area of$995.3~\mu $m2and a quiescent current of 162–974 nA at a 1-V${V} _{\text {DD}}$.

Mixed-signal processing-in-memory (PIM) has gained prominence as a promising approach for implementing deep neural networks in energy-constrained systems. However, the co-design and optimization of mixed-signal circuits in PIM demand substantial time and effort for simulation and validation. This work presents X-PIM, a fast modeling and validation framework for mixed-signal PIMs. X-PIM encompasses not only the precise modeling of transistor-level analog computation circuits in System Verilog but also the rapid validation of system-level neural networks implemented using the mixed-signal PIM model. For achieving both accuracy and speed in simulation, X-PIM introduces a technique called compressed equivalent model (CEM) for the mixed-signal PIM circuits. This technique transforms a two-dimensional PIM array into an equivalent single-cell model. Furthermore, X-PIM can account for the impact of non-ideal operations in mixed-signal circuits by incorporating effects such as ADC quantization noise, parasitic components, intrinsic noise, and finite bandwidth. Based on the proposed mixed-signal PIM modeling, X-PIM can perform the system-level neural network validation with a significantly reduced simulation time at least 200 times faster than that of SPICE-based validation. X-PIM demonstrates three mixed-signal PIMs: XNOR PIM, capacitive PIM, and ReRAM-based PIM. For multi-layer perceptron (MLP) network, X-PIM can complete accuracy evaluation for MNIST-IOOO dataset within only 30 minutes.

This article presents the design of an area/ power-efficient discrete-time (DT) delta-sigma ($\Delta \Sigma $) modulator suitable for multichannel sensor applications. First, the area efficiency of the modulator is achieved by optimizing the size of the sampling capacitor with the compact integrators based on the dynamic-boost inverter (DBI). The DBI is designed to have a small active area of only 0.00044 mm2, due to its self-bias scheme that eliminates the need for additional hardware for biasing circuitry. Second, the power efficiency is improved through the quantitative design approach to reduce the power consumption of the integrators by optimizing the gain–bandwidth product (GBW) of the DBI-based OTA in each integrator. In addition, the static current consumption of the integrators is further reduced due to the power-saving feature of the DBI utilizing the principle of a composite transistor. Finally, the self-bias scheme ensures that the DBI maintains a dc gain of 44.3 dB despite circuit mismatch by balancing the currents of the nMOS and pMOS transistors in the DBI. The prototype modulator, fabricated using 0.18-$\mu \text{m}$CMOS technology, occupies an active area of 0.0939 mm2. For a 25-kHz bandwidth (BW), the modulator achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 84.0 dB, a peak SNR of 85.1 dB, and a DR of 87.1 dB with a power supply rejection ratio (PSRR) of 56.8 dB and a common-mode rejection ratio (CMRR) of 66.1 dB at a 1.8-V supply. The modulator also maintains an SNDR higher than 82.5 dB and a DR higher than 85.5 dB for a 5–25-kHz BW with an${\mathrm {FoM}}_{W}$of 78.4–103.4 fJ/conversion at a 1.5–1.8-V supply.

This article presents a fully passive noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) that can be compatible with dynamic voltage and frequency scaling (DVFS) schemes while offering a 12-bit resolution for Internet-of-Things (IoT) sensor applications. To realize a voltage-scalable suppression of the in-band quantization noise, the proposed ADC utilizes a second-order cascade of integrators with feedforward (CIFF) NS loop with a 3-input dynamic comparator, which can obtain an additional resolution of more than 3 bits. A cyclic dynamic element matching (CDEM) for MSB is seamlessly combined with the NS operation and simply realized by shift registers (SRs). The MSB CDEM reduces dominant in-band harmonic distortions due to capacitor mismatch by not only averaging out but also randomizing the MSB mismatch errors with modulation dither from the CIFF NS loop. In addition, a last-bit majority voting (LMV) technique is applied when resolving the LSB to reduce the comparator noise by half with four additional cycles. With both the LMV and CDEM techniques enabled, the SNR and SNDR are enhanced to 73.3 and 72.3 dB, respectively. The ADC achieves an ENOB of$11.2-11.7$bits with a reconfigurable bandwidth of 10–50 kHz at a supply voltage of 0.6–1 V. The prototype ADC was fabricated using 28-nm CMOS technology, occupying an active area of 0.0575 mm2.

A novel self-capacitance transition sensing method is presented for low-power touch detection using a capacitive touch-screen. While maintaining a voltage level, an additional electric charge is additionally required when a touch-input is newly added; the amount of charge is used for detection. Accordingly, the proposed current mirroring voltage-level regulation (CM-VLR) circuit senses the transition of self-capacitance of the touch-screen and detects motions of the touch-object. Only one CM-VLR cell is used to scan the entire touch-screen. Thus low-power readout and high integrated-circuit area efficiency are achieved. Moreover, the proposed self-capacitance sensing method does not require an offset-calibration step through a charge-sharing-based voltage generation and the offset-coverage capacitor. Fabricated in a 180-nm CMOS process, and the CM-VLR cell occupies 0.12 mm2. At a 120-Hz report rate, the proposed analog front-end (AFE) detects touch-input at a 32-dB SNR while dissipating 2.1 mW.

An optical transmitter for driving a Mach-Zehnder (MZ) Interferometer is proposed which incorporates an alldigital phase-locked loop (ADPLL) and a source-series terminated (SST) driver. The proposed optical transmitter is composed of a pattern generator, a clock synthesizer and a modulator driver. The transmitter for an external modulator should drive a large capacitance with a high voltage swing, which requires both large power consumption and area. In this work, the ADPLL is employed for the clock synthesizer to achieve a small area and low power consumption. A high voltage swing over 2 Vdiff-ppwith low power is obtained by adopting the SST driver. The implemented transmitter occupies only 0.58 mm2with power dissipation of 391.6 mW at operating data rate of 21.6 Gb/s.

A 20 Gb/s source-series-terminated (SST) driver that provides large output swing for optical modulator is presented. This work incorporates a stacked SST driver to enlarge output swing up to 3.6 VPP, Diff. For high-speed operation over 20 Gb/s, the stacked SST driver is implemented with only thin-oxide devices. In addition, a 2-tap feed-forward equalizer (FFE) is employed to offer pre-emphasis that can compensate non-ideal effects in the optical modulator or interconnection. The prototype is fabricated in 65-nm CMOS process. Electrical measurement results show that the proposed driver achieves 3.6 VPP, Diffoutput swing at 20 Gb/s. The power consumption of the prototype is 477 mW with 1.2 V and 2.4 V dual supplies. The prototype occupies 0.24-mm2active area.