Despite the potentially superior phase-noise (PN) performance compared to the parallel-tank resonance oscillator, the series-resonance oscillator (SRO) usually suffers from a narrow tuning range (TR) ofmcells as required for oscillation. Typically, enhancing the TR of SRO requires lowering the tank Q-factor at the cost of PN and figure-of-merit (FoM). This paper proposes a quadrature SRO with an enhanced TR using higher-order tanks with a boosted coupling factor by means of trifilar transformers. This maintains the low PN while improving its tuning range (TR) to 22% (i.e., 10.3 to 12.9GHz). Designed in TSMC 28-nm HPC+ CMOS, as per post-layout full-chip simulations, the proposed SRO achieves PN of -124dBc/Hz and -146dBc/Hz at 1 and 10MHz offset, respectively, from the 12.24GHz carrier frequency, while consuming 55mW. This results in an FoM of 188.3–190.1dBc/Hz and an FoMTof 194.7–197.7dBc/Hz across the TR.

In this paper, we present a fully integrated ring-oscillator (RO)-based temperature sensor for quantum computing applications. As the quantum states exhibit an exponential sensitivity to the on-die cryogenic temperature change, any such temperature variation due to, for example, local heating islands arising from the poor thermal conductivity of silicon should be monitored. For this purpose, we exploit a compact RO sensor placed in the vicinity of qubits. The proposed approach employs four differently sized oscillators and two VBGs to generate, in total, eight different temperature-dependent oscillating frequency signals. Then, by performing their polynomial fitting, a linear temperature-frequency compensating model for the proposed sensor is derived. Fabricated in 22 nm FD-SOI technology, the proposed sensor occupies 0.0016 mm2, consumes 128 μW and achieves maximum inaccuracy of ± 2.1 K in a wide temperature range from 3 to 270 K.

In this paper, we present an inverter-based ring oscillator (RO) operating at cryogenic temperatures for quantum computing applications. It employs a low-dropout regulator (LDO) to provide supply voltage for a programmable switched-capacitor system which isolates the supply line of the integrated RO circuit from any noise or perturbations of the external power supply. In anticipation of embedding the RO into a phase-locked loop (PLL), we study the variation of flicker phase noise from cryo to room temperature by indirectly measuring the phase noise (PN) in the 30dB/dec region. The proposed system occupies 0.012mm2and shows 3.5dB integrated PN improvement thanks to the proposed voltage supply noise reduction technique at room temperature (RT) and the FOM is estimated as 121.7dB at cryogenic temperature (CT).

Gain-cell (GC) based eDRAM has been a promising memory topology due to the lower area footprint and energy consumption than its SRAM counterpart. However, the eDRAM suffers from a short retention time in finer technology nodes. Enhancing the retention time requires both pMOS and nMOS devices, but this inadvertently increases the cell size due to the minimum spacing between them. Further, the retention time is dominated by either logic ‘1’ or ‘0’, lowering the overall retention time. In our work, we propose an nMOS-only GC-based 4T GC-eDRAM memory topology that occupies an area comparable to the 3T GC-eDRAM and enhances the retention time by balancing logic ‘0’ and ‘1’ via controlling the leakage path. Designed in GlobalFoundries 22-nm FD-SOI, the post-layout simulation of a dual port 128×128 (4kb) eDRAM memory array shows 610 μW and 490 μW of write and read power consumption at 250 MHz, respectively, while maintaining the retention time of 25 μs. The 4T bit-cell with the logic design rule only occupies 0.12 μm2, which is 1.5× lower than the two-port 8T SRAM cells in the PDK, while 1.1× larger than the single-port 6T SRAM.

This article presents a wide-band suppression technique of flicker phase noise (PN) by means of a gate–drain phase shift in a transformer-based complementary oscillator. We identify that after naturally canceling its second-harmonic voltage by the complementary operation itself, third-harmonic current entering the capacitive path is now the main cause of asymmetry in the rising and falling edges, leading to the$1/f$noise upconversion. A complete$1/f^{3}$PN analysis for the transformer-based complementary oscillator is discussed. By tuning gate–drain capacitance ratio, a specific phase-shiftrangeis introduced at the gate and drain nodes of the cross-coupled pair to mitigate the detrimental effects of ill-behaved third-harmonic voltage, thus lowering the flicker PN. To further reduce the area and improve the PN in the thermal region, we introduce a new triple-8-shaped transformer. Fabricated in 22-nm FDSOI, the prototype occupies a compact area of 0.01mm2and achieves$1/f^{3}$PN corner of 70kHz, PN of −110dBc/Hz at 1MHz offset, figure-of-merit (FoM) of −182dB at 9GHz, and 39% tuning range (TR). It results in the best FoM with normalized TR and area (FoMTA) of −214dB at 1MHz offset.

This paper presents a simple yet effective$G_{m}$-boosting technique for improving gain and noise performance of millimeter-wave (mm-wave) low-noise amplifiers (LNAs) comprising triple-well transistors typically found in the modern bulk CMOS processes. The proposed technique uses a resistor that connects the p-well and deep n-well terminals of the triple-well transistor, leaving the terminals floating instead of conventionally connecting them to the ground and supply voltage. This arrangement exploits a leakage current through a diode formed between the drain/source and p-well of each transistor, thus autonomously setting its bulk potential for increased transconductance, while ensuring its robustness to the process variation. The improved isolation between the p-well and the substrate further improves the gain and noise performance. We provide a theoretical analysis of this floating resistor-based body biasing method and support it with simulation results. For experimental validation, a two-stage cascode LNA was designed and fabricated in 28-nm bulk CMOS. The measurement results show that 3.3–4dB noise figure (NF) and 19.1–16.1dB gain are achieved at 24.7–29.5GHz. To ensure a fair comparison, another identical LNA with the normally expected triple-well biasing was also fabricated. The proposed method reveals a 0.6dB improvement in minimum NF and an additional ~3.5dB gain without any significant linearity degradation.

We describe a quantum computing hardware paradigm that exploits the current scaling achievements of mainstream CMOS technology. Just like in a small IC chip, where a single nanometer-sized CMOS transistor can be reliably replicated millions of times to build a digital processor, we propose a new structure of a qubit realized as a CMOS-compatible charge-based quantum dot that can be reliably replicated thousands (or perhaps even millions) of times to construct a quantum processor. Combined with an on-chip CMOS controller, it will realize a useful quantum computer (QC) that can operate at 4 K, which is much higher than the temperature of today's QCs of 15 mK.

This paper presents an HDL-synthesized injection-locked phase-locked loop using LC-based DCO for on-chip clock generation. The superior noise performance of the LC-DCO enables the proposed synthesizable PLL to achieve top performance among the existing designs. Fabricated in a 65nm CMOS process, this prototype demonstrates a 0.142ps integrated jitter at 3.0GHz and consumes 4.6mW while only occupying an area of 0.12mm2. It achieves a figure of merit (FoM) of -250.3dB, which is the best for the synthesized PLL up-to-date.

This paper presents an automatic place-and-routed two-stage fractional-N injection-locked PLL (IL-PLL) using soft injection technique for on-chip clock generation. Fabricated in a 65nm CMOS process, this prototype demonstrates a 3.6-ps integrated jitter at 1.5222 GHz and consumes 3mW leading to an FoM of -224.6 dB while only occupying an area of 0.048 mm2. It realizes the first fully synthesized fractional-N injection-locked PLL up-to-date.

This paper presents a low power and low noise sub-harmonically injection-locked PLL using a 20GHz sub-sampling PLL (SS-PLL) and a quadrature injection locked oscillator (QILO). Lower in-band phase noise and out-of-band phase noise have been achieved through the sub-sampling phase detection and sub-harmonic injection techniques, respectively. Implemented in a 65nm CMOS, this work can support all 60GHz channels and achieves a phase noise of -115dBc/Hz at 10MHz offset while consuming 20.2mW and 14mW from the 20GHz SS-PLL and the QILO, respectively.

This paper presents a small area, low power, fully synthesizable PLL with a current output DAC and an interpolative-phase coupled oscillator using edge injection technique for on-chip clock generation. A prototype PLL is fabricated in a 65nm digital CMOS process, achieves a 1.7-ps integrated jitter at 0.9 GHz and consumes 0.78 mW leading to an FOM of -236.5 dB while only occupying an area of 0.0066 mm2. It achieves the best performance-area trade-off.

This paper presents a compact, low power, and low jitter dual-loop injection-locked PLL with synthesizable all-digital background calibration system for clock generation. Implemented in a 65nm CMOS process, this work demonstrates a 0.7-ps RMS jitter at 1.2 GHz while having 0.97-mW power consumption resulting in an FOM of -243dB. It also consumes an area of only 0.022mm2resulting in the best performance-area trade-off system presented up-to-date.

A swing-enhanced current-reuse class-C VCO which can theoretically achieve same phase noise figure-of-merit (FoM) as other class-C VCOs at the lowest power consumption is presented. A swing enhancement in class-C operation and an oscillation robustness are achieved through dynamic bias control circuits for both NMOS and PMOS transistors. The proposed VCO has been fabricated in 180nm CMOS process while oscillating at 4.6 GHz. The measured phase noise is -119 dBc/Hz at 1 MHz offset while consuming 1.6 mA from 1.5 V supply. An FoM of -189 dBc/Hz is achieved.

A 58.1-to-65.0 GHz frequency synthesizer using sub-harmonic injection-locking technique is presented. The synthesizer can generate all 60GHz channels defined by IEEE 802.15.3c, wirelessHD, IEEE 802.11ad, WiGig, and ECMA-387. A frequency calibration scheme is proposed to monitor frequency shift resulting from environmental variations. Implemented in a 65nm CMOS process, the synthesizer achieves a typical phase noise of -117 dBc/Hz @10MHz offset from a carrier frequency of 61.56 GHz.