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Carlos Garcia-Vega

dblp:121/3494 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 2016
0000-0001-9070-8165ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › digital circuit design
arithmetic circuit design
0.212016
Decimal Multiformat Online Addition · IEEE Trans. Computers 2016
Integrated circuit design › digital arithmetic circuits › decimal arithmetic
decimal adder
0.212016
Decimal Multiformat Online Addition · IEEE Trans. Computers 2016
Integrated circuit design
digital circuit design
0.212016
Decimal Multiformat Online Addition · IEEE Trans. Computers 2016

Methods — techniques the papers use, named apart from their topics

synthesis · 0.2code conversion · 0.2
YearPublicationVenuePosition
2016 Decimal Multiformat Online Addition
abstract
This paper presents and analyzes two different strategies for designing multiformat online decimal adders ($\text{olDFA}_{\text{Mformat}}$). The first strategy uses a code conversion stage plus an online Decimal Full Adder (olDFA); the second one involves designing specific adders by modifying the architecture of the olDFA. These strategies are applied in the design of specific architectures to deal with financial analysis calculations. We use synthesis results to verify the theoretical aspects of the designs and to analyze the robustness and lacks of the strategies. The guidelines presented in the paper are valuable to designers of online multiformat-based solutions.
Carlos Garcia-Vega, Sonia Gonzalez-Navarro, Pedro Balboa-La Chica, Julio Villalba
IEEE Trans. Computers1
2012 On-line Decimal Adder with RBCD Representation
abstract
In this paper we present the design of an on-line adder dealing with two RBCD numbers. This basic element is intended to be be used in any on-line system in which the addition is involved. We obtain the on-line adder by serialization of a recent parallel RBCD adder with minimum latency.To reduce the cycle time a pipelined version is proposed. To deal with data stream the throughput has been reduced to its theoretical minimum possible value by a negligible cost hardware modification. Finally, actual implementation results for 16 digits (i.e. decimal64 format) are presented.
Carlos Garcia-Vega, Sonia Gonzalez-Navarro, Julio Villalba, Emilio L. Zapata
ASAP1