Continuous-time (CT) Delta-Sigma-Modulators (DSMs) are widely utilized in systems requiring wide bandwidth and high resolution. While opamp-based RC integrators are favoured for their excellent linearity, they introduce low-input impedance and complicate the ADC driver. On the other side, Gm-C integrators provide high input impedance, making them more power-efficient, but they suffer from non-linearity, thereby limiting the input range. This paper explores the limitations of a specific non-linearity cancellation technique applied in DSM system-level. The principles of this technique are reviewed, and the challenges of using it at low oversampling ratio (OSR) are investigated. A theoretical analysis is presented, matching with simulation results.

Recently, there is an increased demand for high-linearity applications, where the requirements on the base-band Analog-to-Digital Converter (ADC) Spurious Free Dynamic Range (SFDR) represents a challenge. Most ADC architectures suffer from element mismatch which limits the linearity, and require significant calibration, whose resolution is ultimately limiting the performance. The exception is the single-bit Delta-Sigma Modulator (DSM), where the internal Digital-to-Analog Converter (DAC) is intrinsically linear and ideally no calibration is required, making it the architecture of choice in recent high linearity implementations [1]–[3]. However, when the Over Sampling Ratio (OSR) is constrained to low values, the modulator linearity becomes intrinsically limited by the quantized operation of the modulator, even with perfectly linear DAC and ideal components in the loop filter. In this article we focus on this limitation of linearity by the quantizer, discuss how to best model it, and evaluate what are the key elements the designers have to master in order to design for best linearity.

This paper presents a SAR-assisted first order incremental$\Sigma\Delta$analog-to-digital converter (ADC) equipped with an accumulation based sample and hold (S/H) circuit to effectively limit its kT/C noise contribution, potential bottleneck for the resolution performance of the converter. This system has been designed for shunt current measurements in the electrical drives battery management framework; the sensed and digitized current information is needed for a proper monitoring and regulation of the behaviour of these essential devices for automotive applications. The converter has been developed at the behavioural level in the MATLAB Simulink environment with special attention to the S/H circuit which has been analyzed in Cadence Virtuoso; the complete system features a high common mode voltage (HCMV) in the order of tens of Volts, a peak-to-peak 50 mV differential input range and a target resolution of 12 bits.