Resistively switching, non-volatile memory devices facilitate new logic paradigms by combining storage and processing elements. Several non-stateful concepts such as Scouting or Majority have been proposed for the implementation of logic Computing-in-Memory based on active 1T-1R crossbar arrays. The operation reliability of these concepts critically depends on the accurate readout current distinction. In this paper, we perform experimental tests for several non-stateful logic gates based on transistor-coupled resistive devices (further denoted as 1T-1R) using HfOx as the insulating material. The focus of our investigation lies on the operation reliability and the influence of operation parameters. Based on our experimental findings, we conduct a thorough statistical analysis, assessing the reliability and outline the limitations of non-stateful 1T-1R logic functions for Computing-in-Memory.

Emerging non-volatile memories (NVMs) represent a disruptive technology that allows a paradigm shift from the conventional von Neumann architecture towards more efficient computing-in-memory (CIM) architectures. Several instrumentation platforms have been proposed to interface NVMs allowing the characterization of single cells and crossbar structures. However, these platforms suffer from low flexibility and are not capable of performing CIM operations on NVMs. Therefore, we recently designed and built the NeuroBreakoutBoard, a highly versatile instrumentation platform capable of executing CIM on NVMs. We present our preliminary results demonstrating a relative error < 5% in the range of 1 kΩ to 1 MΩ and showcase the switching behavior of a HfO2/Ti-based memristive cell.

Memristive devices offer energy and area efficient non-volatile data storage for data-intense Ternary Content Ad-dressable Memory (TCAM) architectures. However, depending on the storage implementation in the bitcell design, the matching functionality shows multiple undesired discharge effects leading to false look-up results. In particular, the ternary storage suffers during the look-up operation from a poor resistance ratio, match-line leakage and device variabilities. In this paper, we investigate the inherent, design-dependent limitations in the ternary state storage capability due to different memristive TCAM bitcell design parameters and device variabilities. We test these limits based on variability-aware device simulations and isolate crucial parameters for the optimization of memristive TCAMs.

Animals rely on different decision strategies when faced with ambiguous or uncertain cues. Depending on the context, decisions may be biased towards events that were most frequently experienced in the past, or be more explorative. A particular type of decision making central to cognition is sequential memory recall in response to ambiguous cues. A previously developed spiking neuronal network implementation of sequence prediction and recall learns complex, high-order sequences in an unsupervised manner by local, biologically inspired plasticity rules. In response to an ambiguous cue, the model deterministically recalls the sequence shown most frequently during training. Here, we present an extension of the model enabling a range of different decision strategies. In this model, explorative behavior is generated by supplying neurons with noise. As the model relies on population encoding, uncorrelated noise averages out, and the recall dynamics remain effectively deterministic. In the presence of locally correlated noise, the averaging effect is avoided without impairing the model performance, and without the need for large noise amplitudes. We investigate two forms of correlated noise occurring in nature: shared synaptic background inputs, and random locking of the stimulus to spatiotemporal oscillations in the network activity. Depending on the noise characteristics, the network adopts various recall strategies. This study thereby provides potential mechanisms explaining how the statistics of learned sequences affect decision making, and how decision strategies can be adjusted after learning.

The field of neuromorphic computing is approaching an era of rapid adoption driven by the urgent need of a substitute for the von Neumann computing architecture. NEUROTEC I: “Neuro-inspired Artificial Intelligence Technologies for the Elec-tronics of the Future” project is an initiative sponsored by the German Federal Ministry of Education and Research (BMBF for its initials in German), that aims to effectively advance the foundations for the utilization and exploitation of neuromorphic computing. NEUROTEC I stands at its successful “final stage” driven by the collaboration from more than 8 institutes from the Jiilich Research Center and the RWTH Aachen University, as well as collaboration from several high-tech industry partners. The NEUROTEC I project considers the field interplay among materials, circuits, design and simulation tools. This paper provides an overview of the project's overall structure and discusses the scientific achievements of its individual activities.

Memristive devices, such as ReRAM devices, enable Computation-In-Memory operations such as vector-matrix multiplications, which are basic kernels for neuromorphic computing. These devices, however, suffer from parasitic sneak path currents in memory arrays, which make a satisfactory performance on large-scale arrays impossible. To overcome this issue, for example, a bipolar rectifying element (‘select device’) in series to a resistive switching device (1S1R) is introduced at each cross-point junction. In this work, we investigate the design of 1S1R arrays for VMM operations and show the impact of wire resistances on these operations. We derive guidelines that give a quantitative relationship between the array size, wire resistance values, resistance states of the ReRAM and the select device and resulting current levels.

Computation-in-Memory (CiM) with emerging non-volatile memories leads to significant performance and energy efficiency, which is a promising approach to address so-called memory wall of conventional von Neumann architectures. Redox-based Random access memory (ReRAM) is an appropriate candidate for the realization of CiM concepts in CMOS co-integrated crossbar structures. However, ReRAM devices suffer from inherent variability in fabrication and operation. In this paper, we propose a statistical failure probability framework for the reliability evaluation of ReRAM-based CiM. Based on this, a comprehensive reliability analysis is performed for logic operations in ReRAM-based Scouting and MAGIC concepts at the crossbar level. Our proposed framework shows that existing logic operation in the crossbar architecture has a high failure probability due to the variability and crossbar non-idealities. Hence, a modified crossbar design is proposed to achieve the target reliability requirements.

Conventional von Neumann architectures cannot successfully meet the demands of emerging computation and data-intensive applications. These shortcomings can be improved by embracing new architectural paradigms using emerging technologies. In particular, Computation-In-Memory (CiM) using emerging technologies such as Resistive Random Access Memory (ReRAM) is a promising approach to meet the computational demands of data-intensive applications such as neural networks and database queries. In CiM, computation is done in an analog manner; digitization of the results is costly in several aspects, such as area, energy, and performance, which hinders the potential of CiM. In this article, we propose an efficient Voltage-Controlled-Oscillator (VCO)–based analog-to-digital converter (ADC) design to improve the performance and energy efficiency of the CiM architecture. Due to its efficiency, the proposed ADC can be assigned in a per-column manner instead of sharing one ADC among multiple columns. This will boost the parallel execution and overall efficiency of the CiM crossbar array. The proposed ADC is evaluated using a Multiplication and Accumulation (MAC) operation implemented in ReRAM-based CiM crossbar arrays. Simulations results show that our proposed ADC can distinguish up to 32 levels within 10 ns while consuming less than 5.2 pJ of energy. In addition, our proposed ADC can tolerate ≈30% variability with a negligible impact on the performance of the ADC.

In recent years, we are witnessing a trend toward in-memory computing for future generations of computers that differs from traditional von-Neumann architecture in which there is a clear distinction between computing and memory units. Considering that data movements between the central processing unit (CPU) and memory consume several orders of magnitude more energy compared to simple arithmetic operations in the CPU, in-memory computing will lead to huge energy savings as data no longer needs to be moved around between these units. In an initial step toward this goal, new non-volatile memory technologies, e.g., resistive RAM (ReRAM) and phase-change memory (PCM), are being explored. This has led to a large body of research that mainly focuses on the design of the memory array and its peripheral circuitry. In this article, we mainly focus on the tile architecture (comprising a memory array and peripheral circuitry) in which storage and compute operations are performed in the (analog) memory array and the results are produced in the (digital) periphery. Such an architecture is termed compute-in-memory-periphery (CIM-P). More precisely, we derive an abstract CIM-tile architecture and define its main building blocks. To bridge the gap between higher-level programming languages and the underlying (analog) circuit designs, an instruction-set architecture is defined that is intended to control and, in turn, sequence the operations within this CIM tile to perform higher-level more complex operations. Moreover, we define a procedure to pipeline the CIM-tile operations to further improve the performance. To simulate the tile and perform design space exploration considering different technologies and parameters, we introduce the fully parameterized first-of-its-kind CIM tile simulator and compiler. Furthermore, the compiler is technology-aware when scheduling the CIM-tile instructions. Finally, using the simulator, we perform several preliminary design space explorations regarding the three competing technologies, ReRAM, PCM, and STT-MRAM concerning CIM-tile parameters, e.g., the number of ADCs. Additionally, we investigate the effect of pipelining in relation to the clock speeds of the digital periphery assuming the three technologies. In the end, we demonstrate that our simulator is also capable of reporting energy consumption for each building block within the CIM tile after the execution of in-memory kernels considering the data-dependency on the energy consumption of the memory array. All the source codes are publicly available.

Sequence learning, prediction and replay have been proposed to constitute the universal computations performed by the neocortex. The Hierarchical Temporal Memory (HTM) algorithm realizes these forms of computation. It learns sequences in an unsupervised and continuous manner using local learning rules, permits a context specific prediction of future sequence elements, and generates mismatch signals in case the predictions are not met. While the HTM algorithm accounts for a number of biological features such as topographic receptive fields, nonlinear dendritic processing, and sparse connectivity, it is based on abstract discrete-time neuron and synapse dynamics, as well as on plasticity mechanisms that can only partly be related to known biological mechanisms. Here, we devise a continuous-time implementation of the temporal-memory (TM) component of the HTM algorithm, which is based on a recurrent network of spiking neurons with biophysically interpretable variables and parameters. The model learns high-order sequences by means of a structural Hebbian synaptic plasticity mechanism supplemented with a rate-based homeostatic control. In combination with nonlinear dendritic input integration and local inhibitory feedback, this type of plasticity leads to the dynamic self-organization of narrow sequence-specific subnetworks. These subnetworks provide the substrate for a faithful propagation of sparse, synchronous activity, and, thereby, for a robust, context specific prediction of future sequence elements as well as for the autonomous replay of previously learned sequences. By strengthening the link to biology, our implementation facilitates the evaluation of the TM hypothesis based on experimentally accessible quantities. The continuous-time implementation of the TM algorithm permits, in particular, an investigation of the role of sequence timing for sequence learning, prediction and replay. We demonstrate this aspect by studying the effect of the sequence speed on the sequence learning performance and on the speed of autonomous sequence replay.

In this work, TaOx based ReRAM devices were fabricated by reactive sputtering. The impact of RF power on the device characteristics was investigated using five different RF powers ranging from 116 W (RF 20%) to 356 W (RF 60%), resulting in different film deposition rates. Depending on RF power, both the initial device resistance (Rinitial) and forming voltage (Vform) were found to be changed. The switching layer sputtered at 116 W shows the highest Rinitial(80 GΩ), whereas the lowest resistance (50 kΩ) is obtained at 236 W. The device RESET level (Roff) is a function of Rinitialand Vform. The largest memory window (Roff/ Ron~ 105) and 2-bit MLC operation are achieved at 236 W deposition power. These devices show excellent retention at 125 °C for 104seconds and good endurance up to 106cycles. These results reflect the impact of the sputtering deposition power on the electrical performance of the ReRAM devices. It is due to the fact that the structural defects and oxygen content in the deposited film are modulated by the sputtering power.

In this work, we use a Cr-doped V2O3based Mott oscillator circuit to build a reservoir computing system that has much smaller model size than an equivalent LSTM. In contrast to an LSTM, our reservoir computing system can be trained very efficiently and on-line, with very low latency. We demonstrate close to state-of-the-art performance with three benchmark tasks: speech recognition, handwritten digit recognition, and HDD channel decoding. We show that our Mott circuit-based reservoir computing system brings significant reduction in power consumption and inference speed compared to CPU, GPU, or FPGA based systems.

Memristive devices can be exploited for memory as well as logic operation paving the way for non von-Neumann Computation-In-Memory architectures. To validate the potential of such architectures accurate compact models for the memristive devices are required. As a standard device is not available, evaluating the performance of such an architecture is ambiguous. This paper proposes a flexible model for bipolar, filamentary switching, redox-based memristive devices. The model does catch both the device resistance ratio as well as the nonlinearity of the switching kinetics. It is used to perform design exploration for three memristive based circuit design (IMPLY, MAGIC and CRS) for computation-in-memory architectures.

This paper addresses the two main resistive switching (RS) memory technologies: phase-change memory (PCM) and redox-based resistive random access memory (ReRAM). It will review the basic concepts, the initial promises, and current state of the art, with focus on possible scaling pathways for low-power operation and dense, true 3-D memory. Recent physical insights and new potential concepts will be discussed.