Accurate prediction of throughput, measured in Transactions per Second (TPS), is critical for financial trading systems, as it ensures system stability and scalability under high transaction volumes. We address this challenge by introducing a hybrid model that combines Discrete Wavelet Transform (DWT), Convolutional Neural Networks (CNN), and a Gated Recurrent Unit with an Attention Mechanism (GRU-AM). Our approach decomposes the nonlinear, non-stationary TPS data into high- and low-frequency components using DWT, allowing CNN and GRU-AM models to capture dynamic and nonlinear features effectively. Experimental results on real-world trading system data demonstrate the method's effectiveness. Compared to a variety of models, including ARIMA, CNN, and GRU, our method improves prediction accuracy by 2% to 20%. These results underscore the model's enhanced accuracy and efficiency, providing robust support for TPS prediction in financial trading systems.

Abstract The globalization of the integrated circuit design industry makes it easier for the adversary to pirate intellectual property and insert hardware Trojans (HTs). Although many HT protection methods have been proposed, some malicious elements can still be inserted into vulnerable nodes. Trojans are usually inserted in the rare nodes with the lowest observability, which makes it hard for testers to discover them. In this paper, we propose a dual-protection technology to protect the circuit against HT attacks based on observability. First, we propose an algorithm to increase the low observabilities of the circuit, so as to make it difficult for attackers to implant HTs. Several existing approaches try to identify the low observability by setting a threshold artificially, which is not generic. We do not need to set thresholds when targeting the low observability. Second, we present another logic locking algorithm to enhance the entire circuit’s security further. Simulation results on ISCAS85 benchmark and several larger circuits show that the proposed HT protection method has increased the lowest observability of the circuit by an average of 370.76 times. Furthermore, the logic locking technique maximizes the ambiguity for an attacker. Compared with the state of the art, the proposed logic locking can obtain better results, achieving a Hamming distance that is closer to 50% between the correct and incorrect outputs when a wrong key is applied.

Traditional logic synthesis methods are based on Boolean logic, which tends to produce redundant logic structures in dense circuit applications, such as complex number operations and error detection/correction coding. Traditional Boolean and Reed-Muller (TB-RM) logic synthesis method combining traditional Boolean (TB) logic and Reed-Muller (RM) logic can improve comprehensive optimization indexes and reduce cost. The existing TB design method is not effective when dealing with constrained systems with high-resource utilization requirements. In addition, traditional synthesis methods do not consider multiobjective optimization of area, power consumption and reliability. To solve these problems, we propose an effective dual logic synthesis method (EDSM), which includes dual logic detection method (DDM) and differential evolution algorithm based on multidimensional mutation strategy (DE-MMS). DDM can complete the logic detection function, and DE-MMS can further optimize the polarity. In addition, to evaluate the soft errors occurring more efficiently at the logic level, we propose a soft error rate (SER) estimation model. Experimental results show that compared with state-of-the-art evolutionary algorithms, EDSM can search for optimal solutions in all optimization problems; compared with commonly used TB-based minimization methods, EDSM has obvious advantages in multiobjective optimization of area, power consumption and SER. After 6-LUT FPGA technology and standard cells mapping, by selecting area as the optimal cost implementation, we obtain average improvements in the area of 14% and 2%, respectively.

Area and reliability optimization have become the primary constraints in circuits logic synthesis. To address the increasing area and transient fault susceptibility in combinational circuits, we propose a high-dimensional genetic algorithm (HGA). HGA adopts an evolutionary scheme based on ternary tree, and uses adaptive crossover operator and flight operator to jump out of local optimum. Moreover, based on the HGA, we propose an area and reliability optimization method (AROM) for mixed polarity Reed-Muller logic circuits, which searches the best polarity with minimum area and soft error rate. The experimental results confirm that AROM can search for more desirable nondominated solutions in less time compared to existing optimization methods, and can be used as an effective electronic design automation tool for multi-objective optimization.

The identification of reliability-critical input vectors (RCIVs) is vital in the assessment and prediction of reliability boundaries for logic circuits. This article introduces an approach grounded in association rule analysis (ARA) to swiftly and efficiently identify RCIVs in both combinational and sequential circuits. The utilization of the ARA model for validating the circuit’s associated primary inputs enhances accuracy while simultaneously reducing the complexity of RCIVs identification. Orienting the generation of new samples with associated inputs expedites the identification process. Quantifying circuit complexity enables the adaptive assignment of algorithmic parameters to circuits of diverse sizes. The construction of input sets facilitates a precise evaluation of the reliability of individual input vectors in sequential circuits. Experimental results on benchmark circuits illustrate that this approach achieves a mean accuracy of 0.9952, with Monte Carlo (MC) method serving as the reference, for small and medium-sized circuits, and require only 20.71% of MC’s time overhead. The average coverage of 0.9884 surpasses the reference method by 1.8 times. The stability is 4.35 times higher with the random method on large scale circuits with 224,624 gates and 6,642 primary inputs. Circuit designers can swiftly ascertain the average reliability and reliability boundaries of a circuit by using this approach for RCIVs identification. By applying optimizations of the identified RCIVs to expedite convergence and mitigate fluctuations, the influence of these RCIVs can be minimized in reliability evaluation and testing.

Detecting dense small objects (DSOs) of varying scales still remains a challenging research problem in remote sensing imagery (RSI). Due to their weak feature extraction capabilities for small objects, most existing detection approaches struggle to handle the high proportion of DSO in RSI, thereby increasing the likelihood of missed detections. In addition, the close proximity and overlap of multiscale objects further complicate detection due to occlusion between bounding boxes. In this study, we systematically propose a novel loss function, remote sensing dense small target detection (RSDS), for detecting DSO in RSI, which contains three main components. The first is Gaussian reassignment loss (GRL), which adaptively redistributes sample weights to prevent any single sample (such as positive, negative, easy, and hard samples) from dominating the overall loss. To solve the zero-loss issue in traditional intersection over union (IoU) and intersection over ground truth (IoG) metrics when object boxes do not intersect, we design the Gaussian Wasserstein distance (WD) penalty loss, which models the eligible 2-D detection boxes as Gaussian distributions and calculates the similarity between them. The final one, which we called the occlusion box interaction loss, explains the attraction between DSO and the repulsion from their surroundings. Deploying RSDS not only significantly reduces the probability of missing DSO in RSI, but also enhances the detection accuracy in other similar computer vision tasks. Experiments on the HRSID, NWPU-10, and SSDD datasets show that some general models incorporating RSDS achieve precision improvements of 6.68%, 11.52%, and 5.26%, and 8.71%, 5.17%, and 9.34% in$\text {mAP}_{0.5}$and$\text {mAP}_{0.5\text {:}0.95}$, respectively, compared with other baselines. The code will be found athttps://github.com/CCC0090/RDSD-Loss.

Power optimization can reduce heat dissipation costs and has become an important step of circuit logic synthesis. Because the power optimization for mixed polarity Reed–Muller (MPRM) circuits is a combinatorial optimization problem, in this paper, we first propose a multilevel adaptive memetic algorithm (MAMA), which includes global exploration optimizer, local heuristic optimizer, and initial population optimizer. We use the proposed differential evolution optimization, simulated annealing optimization, and data matching algorithm to make the population evolve. Moreover, based on the proposed matrix decomposition strategy and parallel polarity conversion algorithm, we propose a power optimization approach (POA) for MPRM circuits, which searches for an MPRM circuit with a minimum power using the MAMA. Experimental results demonstrated the effectiveness and superiority of the POA in optimizing the power of MPRM circuits.

In recent years, transformer-based networks, known for their ability to model long-range dependencies, have been widely used in downstream computer vision tasks, surpassing certain neural network architectures. However, transformer-based networks suffer from issues such as large parameter size, high computational complexity, and difficulties in extending spatial and channel features to the third or even higher orders, resulting in convergence challenges for small to medium-sized datasets and limited effectiveness in extracting high-order detailed features. In this paper, we propose a high-order spatial and channel controllable convolution module, named CSn, which can replace standard convolutions in any convolutional network. In the context of remote sensing small object detection, CSndemonstrates superior performance compared to Self-Attention structures embedded in neural networks. Moreover, it introduces long-range dependency relationships among pixels, similar to Self-Attention, and adopts a cascaded recursive approach to extend spatial and channel features to arbitrary higher orders without introducing significant additional computation. This extension captures crucial information from high-order spatial and channel dimensions, resulting in improved accuracy for small object detection. Additionally, we construct a novel, versatile CSn-(FPN+PAN) structure for object detection networks, referred to as CSnNet. Finally, our proposed model exhibits significant advantages in remote sensing detection when compared to state-of-the-art methods on publicly available SAR datasets (SSDD, HRSID) and optical remote sensing dataset (NWPU-10), achieving respective improvements of 3.4%, 4.5%, and 0.4% in mAP50compared to baseline models.

Area optimization is one of the most important contents of circuits logic synthesis. The smaller area has stronger testability and lower cost. However, searching for a circuit with the smallest area in a large-scale space of polarity is a combinatorial optimization problem. The existing optimization approaches are inefficient and do not consider the time cost. In this paper, we propose a multi-strategy wolf pack algorithm (MWPA) to solve high-dimension combinatorial optimization problems. MWPA performs global search based on the proposed global exploration strategy, extends the search area based on the Levy flight strategy, and performs local search based on the proposed deep exploitation strategy. In addition, we propose a fast area optimization approach (FAOA) for fixed polarity Reed-Muller (FPRM) logic circuits based on MWPA, which searches the best polarity corresponding to a FPRM circuit. The experimental results confirm that FAOA is highly effective and can be used as a promising EDA tool.

With the emergence of the multicore architecture and the increase of chip operating frequency, power optimization has become a key step of circuit logic synthesis. Aiming at the XNOR/OR circuits, with the goal of minimizing power, construct the optimal polarity fixed-polarity Reed–Muller (FPRM) circuits power optimization scheme. However, the power optimization for FPRM circuits is a multipeak combinatorial optimization problem, we first propose a metaheuristic optimization algorithm (MOA), which includes the global exploration optimizer, local deep exploitation optimizer, and initial population and uses the proposed differential evolution optimization, fierce wolf siege algorithm-based tabu search, and improved skew tent map to make the population evolve. Based on the proposed Huffman tree construction algorithm and MOA, we propose an efficient power optimization approach (EPOA) to find the minimum power FPRM circuit. Experimental results on the benchmark circuits confirm the effectiveness of EPOA.