Device authentication protocols based on a strong physical unclonable function (PUF) show promise for enhancing Internet of Things security. However, a strong PUF is vulnerable to machine learning (ML) attacks. This paper proposes a Feistel structure sequential obfuscation-based PUF (Feistel-PUF) to resist ML attacks. When the PUF is obfuscated by the Feistel structure, the challenge-response relationship resembles that of sequential logic circuits. Specifically, each response depends on both current and historical challenges, thereby significantly increasing the complexity of the challenge-response mapping. Experimental results showed that even with 1 million collected challenge response pairs, the prediction accuracies of ML attacks on Feistel-PUF remained at approximately 50%. Notably, the obfuscation process excluded response data, thereby preserving the randomness, reliability, and uniqueness of PUF with negligible performance degradation. The Feistel structure was iteratively reused for sequential obfuscation processing, maintaining constant and minimal hardware overhead. We propose a novel approach that combines the Feistel-PUF with an authentication protocol. This system synchronizes obfuscation parameters during the initial registration phase and implements dynamic updates throughout the authentication process. This approach allows the obfuscation structure to be made public, thereby overcoming the reliance on structure or algorithm secrecy in traditional dynamic challenge obfuscation schemes. The security of the protocol was confirmed by subjecting it to ProVerif verification and security analysis.

Freeform thin-shell surfaces are critical in various fields, but their fabrication is complex and costly. Traditional methods are wasteful and require custom molds, while 3D printing needs extensive support structures and post-processing. Thermal shrinkage actuated 4D printing is an effective method for fabricating 3D shell. However, existing research faces issues related to precise deformation and limited robustness. Addressing these issues is challenging due to three key factors: (1) Difficulty in finding a universal method to control deformation across different materials; (2) Variability in deformation influenced by factors such as printing speed, layer thickness, and heating temperature; (3) Environmental factors affecting the deformation process. To overcome these challenges, we introduce FreeShell, a robust 4D printing technique that uses thermal shrinkage to create precise 3D shells. This method prints triangular tiles connected by shrinkable connectors using a single material. Upon heating, the connectors shrink, moving the tiles to form the desired 3D shape, simplifying fabrication and reducing material and environment dependency. An optimized mesh layout algorithm computes suitable printing structures that satisfy the defined structural objectives. FreeShell demonstrates its effectiveness through various examples and experiments, showcasing precision, robustness, and strength, representing advancement in fabricating complex freeform surfaces.

Physically unclonable functions (PUFs) have significant potential in the field of information security applications. To reduce the area of PUF cells and improve the utilization of the PUF entropy source, a dynamic division multiplexing bistable PUF with independent output response is proposed. Initially, a bistable PUF model is constructed by dividing traditional cross-coupled bistable PUF cells. The pull-up (pull-down) network employs large transistor sizes to minimize process variations, while the pull-down (pull-up) network, as the main PUF entropy source, utilizes the minimum transistor size to maximize random process variations. Subsequently, a cross-coupled twin cell with a symmetrical structure and shared word lines is designed, and a PUF cell array is composed ofntwin cells. Finally, the PUF cell array is dynamically configured using the output signal from a decoder. In this configuration, a single selected cell (with large deviation) and$n-1$unselected cells connected in parallel (with negligible deviation) collectively form a bistable PUF circuit for dynamic division multiplexing. The proposed PUF can operate in two independent modes, each of which can generate a 2304-bit feature key. The design is fully customized using the Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm process, and the area (feature size) of a twin cell is only$1.32~\mu $m2(308 F2). Chip test results demonstrated that the proposed PUF achieved the entropy of 0.9999 (0.9997), the uniqueness of 49.9% (49.7%), and the reliability of 99.1% (97.7%) in the Ncell PUF (NC-PUF) [Pcell PUF (PC-PUF)] mode, respectively.

This research presents an original and efficient elite archive-assisted adaptive memetic algorithm (EAMA) to deal with a realistic hybrid differentiation flowshop scheduling problem (HDFSP) with the objective of total completion time minimization. In this scheduling problem, each job consists of multiple parts and the jobs are divided into different types. The manufacturing of a job is comprised of three consecutive stages: 1) parts fabrication on first-stage parallel machines; 2) parts assembly on second-stage single machine; and 3) job differentiation on one of third-stage dedicated machines. We provide a mixed-integer programming model, derive three lower bounds, and further present the EAMA metaheuristic for HDFSP. The EAMA is initialized heuristically, and its global exploration is performed by a differential evolution, which includes three newly designed operators: 1) elite-driven discretized differential mutation; 2) probability crossover; and 3) biased selection. To enhance the local search, an external elite archive is set and evolved in parallel with global exploration by a meta-Lamarckian learning-based adaptive multistage local search and a variable length-based adaptive block-insertion local search. After the global exploration and local exploitation, an elite sharing strategy is used to exchange the excellent information between population and elite archive, and an adaptive restart strategy is used to diversify the population. The influence of parameter setting on EAMA is surveyed by using an improved design-of-experiment. The statistical results from extensive computational experiments demonstrate the effectiveness of the special designs and show that EAMA performs more efficient than the existing algorithms in solving the problem under consideration.

This study presents a technique for designing a multimode configurable weak physically unclonable function (PUF) for security-key generation. The PUF cell is based on the maximum gain point deviations of bias-voltage-controlled inverters. By implementing a preselection strategy, the proposed PUF can simultaneously expose all unstable cells under normal voltage and temperature. Owing to the configurable bias circuit, the PUF cell can be biased at three operating modes, namely, traditional inverter (INV), current-starved inverter (CSI), and power gating (PG). The measurement results from a 65-nm prototype show that the proposed PUF has the following outstanding features: 1) it has a compact cell layout with a minimum feature size of 966 F2; 2) an autocorrelation function of 0.0099 is achieved; and 3) all unstable cells can be eliminated using a preselection procedure, which can drastically reduce the energy and area costs for error correction. In addition, in the CSI mode, the proposed PUF (standard voltage) has maximum frequency and throughput of 714 MHz and 45.7 Gb/s, respectively. Meanwhile, under the INV mode, the worst native bit error rate (low voltage) for 5000 evaluations is only 0.33%, indicating a desirable instability against voltage and temperature variations with a sensitivity coefficient of 1.85%/V and 0.018%/°C, respectively. Moreover, the measured energy efficiency at 0.6 V is 6.83 fJ/bit. Finally, under the PG mode, the standby powers at 0.6 and 1.2 V are only 18 and 86 nW, respectively.

This article presents a novel class of bistable physically unclonable functions (PUFs) for security-oriented applications. The traditional cross-coupled bistable PUF cell is divided into P-net and N-net, wherein the P-net (N-net) multiplexing acts as the shared head (foot), and the N-net (P-net) duplicating multiple acts as the PUF cell. The proposed PUF was fabricated in a Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm process with full-custom design. It can parallelly generate 128-bit identifications (IDs) in one clock cycle owing to the random access word-level readout framework. The measurement results show that the randomness and uniqueness of the proposed PUF are consistent with those of the state-of-the-art works. In addition, the proposed PUF has the following features: 1) the PUF cell is composed only of four nMOS transistors with a minimum feature size of 215-F2; 2) the native bit instability at the golden condition (i.e., 1.2 V, 25 °C) with 500 evaluations is only 2.05%, showing a desirable native stability against supply noise; 3) the bit-error-rate dependences of the voltage and temperature are 3.35%/V and 0.011%/°C, respectively, with the voltage varying within the range 1.0-1.4 V and the temperature varying within the range -40 °C to 125 °C; 4) an autocorrelation function of 0.0049 at a 95% confidence level is achieved and is the lowest reported value to date; and 5) the energy efficiency and throughput at the maximum operating frequency (i.e., 433 MHz) are 99.48 fJ/b and 55.5 Gb/s, respectively.