The effect of the signal transition variation, due to the signal transition density, data asymmetry, and sinusoidal modulation, on the performance of the data transition tracking loop (DTTL) symbol synchronizer is addressed. These factors will affect the DTTL performance, such as the clock jitter and the cycle slippage rate, and unnecessary system loss may result if the system parameters are not well selected. Given the background of C. S. Tsang and W. C. Lindsey (1986), this result can serve as an engineering design guideline for the DTTL in the context of the signal transition variation.>

Bit synchronization in the presence of asymmetric channel noise has not appeared in the open literature. It is the purpose of this paper to study the tracking performance (clock jitter and cycle slip rate) of a popular digital clock synchronizer, the digital data transition tracking loop (DTTL), in the presence of asymmetric noise. Related parameters of interest, the transition density and data asymmetry, are also included. Acquisition performance (frequency acquisition time) is discussed in the absence of noise. A comparison of the DTTL and crossspectrum synchronization loop (CSSL) is also provided. Numerical results are Presented for the design of a bit synchronizer in this environment.

The purpose of this paper is to present a model and associated analysis of the deleterious effects which both transmitter and receiver data clock time-base instability have on bit-error probability. The types of time-base instability modeled and analyzed include what is commonly referred to as bit jitter (epoch jitter), bit-jitter rate (time interval jitter), and data asymmetry. The biterror probability is determined as a function of the statistical characteristics of the time-base instability, the data-transition density, the signal-to-noise ratio in the bit-rate bandwidth and the mechanizations of both the data-bit detector and bit synchronizer. The latter is manifested through the bit synchronizer's natural frequency and loop-damping parameters. Numerical results which indicate the sensitivity of the system bit-error rate to various parameters of the model are provided.