This work demonstrates the potential of a proposed Large language model (LLM) aided front-end design flow in the early development of verified Register Transfer Level (RTL) design. The proposed framework consists of three task-specific LLMs that generate RTL description, test-bench, and review the design to suggest required modifications depending on the simulation results feedback into the model. The proposed framework has been implemented twice with two different versions of OpenAI LLM viz. GPT-3.5-turbo and GPT-4o-mini. Each implementation has been used independently for developing ten distinct designs of different complexities. The results show that low-complexity designs get generated within a few minutes with fewer feedback or review iterations, moderate complexity designs require more time and iterations as compared to low-complexity designs. However, developing a highly complex design is a bit tricky task. Experimental results show that the proposed framework achieves a higher success rate compared to state-of-the-art methods, automatically fixing various types of bugs when simulation results are fed back into the model. Notably, the framework achieves a 90% success rate with GPT-4o-mini and 84% with GPT-3.5-turbo, demonstrating its robustness across different model configurations.

Manufacturing defects need to be detected and diagnosed with the help of on-chip test infrastructure. Scan chains are the most important part of the test infrastructure in the modern designs. However, these scan chains also turn out to be crucial defect locations requiring a diagnosis procedure that has severe implications on debug time and root-cause discovery. These problems are further exacerbated by the compression mechanism present in the test infrastructure. Diagnosis methods proposed in the literature mainly suggest techniques based on fault type-based dictionary computation, simulation with input diagnostic patterns and the subsequent analysis of error responses against the inputs. However, these methods do not take into account the advanced test compression infrastructure. In this work, we propose a diagnosis methodology that is based on state-of-the-art multi-embedded deterministic test (EDT) architecture. We utilize deep learning-based analysis methodology for the purpose of identification of the faulty EDT section based on the observed output responses. Experimental results indicate that with lesser overhead in debug time and resources, the proposed methodology can diagnose faulty EDT with a success rate of 85-90%.

Deep learning accelerators play a crucial role in accelerating the performance of deep neural networks. As these accelerators become more complex, ensuring their correctness and reliability becomes increasingly challenging. Formal verification techniques offer a systematic approach to rigorously validate the design and verify its functional correctness. In this case study, we present a detailed analysis of verifying an open-source deep learning accelerator design (at RTL abstraction), highlighting the methodology, challenges, steps and outcomes of an enhanced formal verification process.

Manufacturing of integrated circuits at the smaller technology nodes leads to several defects in them that must be screened and appropriately diagnosed for minimization of cost overruns. A substantial portion of the functional failures during the process of manufacturing test is often attributed to the defects inside the scan chains. With the advancements in the digital test technologies, almost every chip is manufactured with in-built pattern compression infrastructure. This exacerbates the problem of scan chain diagnosis from the collected failure traces. In this work, an automated methodology to perform this diagnosis in the presence of multiple faults is proposed. Deep learning is utilized to predict the probable candidate locations given the compressed scan chain response. Experiments have been performed on different fault models. Experimental results indicate that the proposed methodology is able to perform the diagnosis with a success rate of approximately 80-100%.

Hardware accelerators have gained immense popularity in recent times for a varied range of healthcare applications. With the growth of edge computing, a large number of sensors can be integrated to enable lightweight computing for processing information. Over the years, there has been significant improvement in deep learning algorithms that offer exciting opportunities for their deployment even in safety-critical biomedical and healthcare applications. A detailed review and discussion on multiple challenges in the design of hardware acceleration catering to healthcare applications are presented in this paper. A wide range of generalized novel architectures and devices offers certain distinct advantages over the conventional processing units. Despite this development, the power and resource constraints of these platforms create significant hindrances in the acceleration of these high-risk medical applications. An elaborate analysis of the range of solutions to overcome these obstacles as well as a perspective on the need to address reliability and security concerns are presented. An alternative correct-by-construction accelerator design methodology is also proposed.

Effective bug localization during verification is a challenging step in the development cycle of complex hardware designs. While meeting different coverage goals is possible in the verification process, yet bug localization cannot be directly related to such goals. We propose a two-step methodology to achieve fine-grained design bug localization. First, we obtain multiple error traces based on a failing property. Starting from an initial error trace, we employ model checking to generate supportive error traces that are utilized to mine important assertions. In the second step, we utilize these assertions for fine-grained design bug localization. The mapping of the assertions leads to specific regions in register transfer level descriptions that are highly probable to be the root cause of the design bug. Specifically, we devise a binning methodology to categorize multiple suspects in different bins that need to be investigated by the design engineer for arriving at the correction for corresponding bugs. Experiments on multiple designs illustrate the efficacy of the proposed methodology in comparison to previous work and state-of-the-art industrial tool.

Design debugging is one of the most important steps in the modern integrated circuits (ICs) development cycle. Simulation-based verification is never sufficient for ensuring design correctness because of its incomplete nature. Formal techniques such as model checking promise to solve this issue through a complete state-space traversal approach. However, because of increasing design complexity, such methods suffer from scalability issues. Guidance-based state-space traversal techniques have been proposed in the past to assist the model checkers in overcoming the complexity bottleneck. Automatically identifying these guidance hints is relatively difficult and requires heuristic-based reasoning procedures. Additionally, to come up with quick fixes during the debug stage, an effective bug localization strategy is needed. In this article, we revisit the paradigm of guidance-based model checking and propose a methodology to improve these guidance generation mechanisms for achieving fine-grained bug localization. In particular, this work proposes a systematic methodology to localize the buggy RTL lines from the erroneous RTL simulation trace. The proposed technique involves the mining of invariant-like assertions from simulation traces. The mined assertions act as probable guidance candidates for the model checking exercise. To identify useful guidance hints from possible ones, we use the Bayesian networks that explore conditional dependence between the various hints at different levels and the target property. These guidance hints are utilized for obtaining possible buggy subregions, which are analyzed via an iterative model checking methodology for fine-grained bug localization. By using the proposed framework, bugs can be localized to within a few lines of RTL description.

The remarkable predictive performance of deep neural networks (DNNs) has led to their adoption in service domains of unprecedented scale and scope. However, the widespread adoption and growing commercialization of DNNs have underscored the importance of intellectual property (IP) protection. Devising techniques to ensure IP protection has become necessary due to the increasing trend of outsourcing the DNN computations on the untrusted accelerators in cloud-based services. The design methodologies and hyper-parameters of DNNs are crucial information, and leaking them may cause massive economic loss to the organization. Furthermore, the knowledge of DNN’s architecture can increase the success probability of an adversarial attack where an adversary perturbs the inputs and alters the prediction. In this work, we devise a two-stage attack methodology “DeepPeep,” which exploits the distinctive characteristics of design methodologies to reverse-engineer the architecture of building blocks in compact DNNs. We show the efficacy of “DeepPeep” on P100 and P4000 GPUs. Additionally, we propose intelligent design maneuvering strategies for thwarting IP theft through the DeepPeep attack and proposed “Secure MobileNet-V1.” Interestingly , compared to vanilla MobileNet-V1, secure MobileNet-V1 provides a significant reduction in inference latency (≈60%) and improvement in predictive performance (≈2%) with very low memory and computation overheads.

Incorporating on-chip trace buffers (TBs) helps to overcome the limited observability by tracing selected signals during post-silicon validation. The effectiveness of TB-based techniques largely relies on selection of appropriate trace signals. For processor-based systems, the selection becomes relatively easier because important signals can be identified. However, for a general digital block in a complex system-on-chip, recognizing necessary trace signals becomes extremely challenging and requires a systematic approach. Previous research on trace signal selection has mainly focused on improving reconstruction of unknown signal values with the help of traced signals. Even though it serves as a good selection principle, an effective signal selection must consider other important factors such as error detection (ED) with the traced signals, which in turn assist in localization and root-cause discovery. Additionally, from practical point of view, the signal selection algorithm needs to cater to factors like routing congestion and minimizing routing wire length. The proposed methodology of signal selection attempts to combine these three crucial factors of signal selection: restoration of untraced signal states, ED with traced signals and routing considerations. The concurrent maximization of all these three parameters is difficult as they have conflicting preference of the candidate trace signals. Hence, the proposed signal selection approach presents a methodology of judiciously mixing the choices of these three objectives. Furthermore, the restored and traced signal states are analyzed for the purpose of error localization at the gate level for several design error models.

Silicon debugging is carried out in multiple sessions which are characterized by run-and-halt intervals. One of the important criteria for the success of this method is that the debugging infrastructure should capture only the erroneous data which can add important insights to the debugging process. However, identification of such suspect clock cycles is not a trivial exercise and requires an systematic approach. We propose a debugging architecture for enhancing the multisession procedure using the technique of on-chip debug data compression. The first session assists in identifying those erroneous clock cycles, and the useful debug data are collected in the second session with the help of markers called tag bits. At the cost of a minimal increase in area overhead, the proposed architecture achieves finer temporal visibility expansion because of the debug data collection in a segregated manner. During the offline analysis of the collected debug data, error localization can be achieved to a finer resolution. We evaluate our methodology on several designs for different kinds of error configurations. Experimental results show that the proposed methodology can achieve better on-chip storage utilization and the expansion in the temporal observation window compared to similar techniques in the literature.

Modern chip multi-processors (CMP) inevitably require cache coherence mechanisms for their correct operation. However, exhaustive functional verification of a complex cache coherence mechanism is a challenging task. This leads to bugs escaping to the first silicon and necessitates validation at the post- silicon stage. In this work, an on-chip signal logging method is proposed which helps in bug detection in case of design errors and soft-errors arising out of reliability issues. The logged contents can then be further dumped off-line for fine-grained bug localization. The proposed methodology utilizes cache coherence protocol specifications to obtain the signal states of coherence transactions and the detector module flags an error once a mismatch is found between observed signal states and correct signal states. The proposed logging mechanism decreases the error detection latency at minimal area and power overheads. Experiments on a four core multiprocessor having a 7-stage MIPS pipeline implementing the widely utilized directory-based MESI protocol indicate that the proposed methodology succeeds in detecting design errors. Analysis of soft errors have also been performed and shorter error detection latency is achieved compared to a previously proposed technique in the literature.

Model checking of large designs is a challenging task because of different scalability issues. In this paper, we aim to utilize guided state space traversal to address this issue. However, providing guidance for state space traversal of complex designs is also an equally challenging problem. We adopt a simulation-based strategy combined with Bayesian modelling approach for finding effective guidance hints for state space traversal. A heuristic-based structural dependency of the design yields ineffective guidance hints which need further of filtering. To prune out the ineffective guidance hints, we first generate module-level sub-properties from static analysis of the design. These sub-properties and structural dependency-based guidance hints are analyzed in simulation traces generated from the constrained-random test benches. These conditional occurrence of sub-properties and guidance hints are inputs to a Bayesian model which can then provide us the guidance hints with the highest profitability. With the proposed methodology, we succeed in pruning out the set of unprofitable guidance hints and obtain effective search directions which are then used to assist the model checking procedure. Experiments on two complex designs for different properties show the effectiveness of the proposed methodology in reducing CPU time during model checking.

Persistent growth in design complexity has led to increased chances of bugs appearing during post-silicon validation. Debugging errors at this stage requires some arrangement for expanding the observability of internal signals of the design. Limited number of trace buffers help in increasing visibility of these internal states. However, appropriate trace signal selection is very difficult. Restorability of untraced states with the help of traced ones is a popular approach for signal selection although it fails to address the main issue of error detection. We propose a signal selection methodology which combines the restoration capability and error detection ability of these signals. Experimental evaluation of the proposed signal selection approach on benchmark circuits indicates improved error detection for various kind of design errors. Practical consideration like minimizing routing overhead has also been analyzed.

Due to tremendous growth in complexity of modern designs, bugs inevitably escape the pre-silicon verification stage. This has led to considerable increase in the time and effort dedicated to post-silicon validation. Debugging designs at postsilicon stage faces a severe bottleneck of limited observability of the internal states. This paper presents a methodology for post-silicon debug utilizing the special features of progressive random access scan (PRAS). The PRAS offers a read-out of nondestructive scan values which is the bottleneck in the process of debugging. The proposed methodology avoids the large overhead of additional resources for debugging as the DfT architecture is reused. PRAS provides a simultaneous solution to the problems of power, data volume and application time during testing at the cost of routing overhead. The PRAS based proposed architecture offers visibility of internal states in fewer clock cycles than traditional serial scan chain based debug methods. The proposed debug scheme offers reconfigurability which enables selective visibility of internal states of a certain portion of the design. Experimental results indicate the better performance of the proposed methodology as compared to the state restoration based observability enhancement techniques.

Drastic growth in design complexity of VLSI circuits has increased the chances of bugs escaping to first released silicon. This has resulted in an increased emphasis on post-silicon validation and debug which is typically hindered by limited observability of internal signals. Trace buffers assist in curbing this bottleneck by storing selected signal states for limited clock cycles. For efficient use of these on-chip buffers, devising a proper selection criterion is of utmost importance. Maximization of restoration of untraced signals is a widely utilized signal selection metric. However, this approach has been seen to not be very effective for error detection. This paper proposes a trace signal selection technique based on error transmission, taking into account the topology of the design. The proposed signal selection methodology can be effectively applied to trace as well as a combination of trace and scan based observability techniques. Experimental evaluation of the proposed methodology on different design errors indicates improvement in error detection as compared to restorability based selection techniques.