Low operating voltage, high storage density, non-volatile storage capabilities, and relative low access latencies have popularized memristive devices as storage devices. Memristors can be ideally used for in-memory computing in the form of hybrid CMOS nano-crossbar arrays. In-memory serial adders have been theoretically and experimentally proven for crossbar arrays. To harness the parallelism of memristive arrays, parallel-prefix adders can be effective. In this work, a novel mapping scheme for in-memory Kogge-Stone adder has been presented. The number of cycles increases logarithmically with the bit width N of the operands, i.e., O ( log 2 N ), and the device count is 5 N . We verify the correctness of the proposed scheme by means of TaO × device model-based memristive simulations. We compare the proposed scheme with other proposed schemes in terms of number of cycle and number of devices.

Redox-based resistive switching devices are an emerging class of non-volatile ultra-scalable memory and logic devices. These devices offer complex internal device physics leading to rich dynamical behavior. Memristive device models are intended to reproduce the underlying redox-based resistive switching device behavior accurately to enable proper circuit simulations. A specific feature of resistively switching devices is the controllability of multi-level resistive states by using a current compliance during the SET operation. Here, we consider a one-transistor-one-resistive-switch circuit to study the multi-level capability of three different types of memristive models. The feasibility of current compliance induced multi-level resistance state control is a check for the accuracy of the memristive device model.

Memristive devices enable non-volatile data storage and in-memory computing capabilities. By using stateful logic approaches, hybrid CMOS nano-crossbar arrays offer additional functionalities such as arithmetic operations. To enable storage and computing on large-scale arrays, parasitic current paths within the array must be avoided. Therefore, for example, a complementary resistive switch (1CRS) or a bipolar rectifying element (‘selector’) in series to a resistive switching device (1S1R) is required at each cross-point junction to suppress low-ohmic sneak paths. In this work 1S1R arrays are considered. First, the in-memory adder concept, initially developed for CRS arrays, is adjusted for a 1S1R array. After that an optimized design is presented and verified by means of memristive simulations. Third, the energy consumption of both concepts is evaluated as a function of array size, and the delay of memristive adder designs are compared quantitatively.

Passive nano-crossbars arrays are highly attractive structures which enable ultra dense non-volatile memories, novel logic-in-memory approaches, and efficient synaptic connections for neuromorphic computing approaches. The basic junction element is a memristive element, i.e. a non-volatile two terminal resistively switching device. In conjunction with a select device paradigm large-scale arrays are feasible.

Integration density is a major drawback of today's associative memories required for intelligent data processing for such as pattern recognition or classification. Ultra dense complementary resistive switch-based architectures are thought to overcome this issue, offering a footprint of 4F2. Here we demonstrate the feasibility of an 8 by 16 associative capacitive network.

Highly predictive memristive models of resistive switches are required to simulate the behavior of anti-serially connected resistive switches, so called complementary resistive switches (CRSs). As an emerging non-volatile device suited for ultra-dense memory architectures, CRS cells offer great potential also as content addressable memories. Here, we introduce a circuit model for TaOx-based resistive switches which we implemented in VerilogA. This model is capable of predicting CRS behavior correctly.

Many memory candidates based on beyond complementary metal-oxide-semiconductor (CMOS) nanoelectronics have been proposed, but no clear successor has yet been identified. In this paper, we offer a methodology for system-level analysis and address the relationship of the maximum performance of a given memory device type to device physics. The method is illustrated for the classical dynamic RAM (DRAM) device and for the emerging memory device known as the resistive RAM (ReRAM).