The major challenge with wide-bandgap (WBG) device-based power electronic converters is the electromagnetic interference (EMI) associated with them. This demands EMI filters, which are often bulky in size, causing lower power density. As a solution, the widely used frequency dithering techniques in literature to reduce EMI noise and filter size often do not consider the effect of Resolution Bandwidth (RBW), causing the violation of international standards. This paper proposes a non-uniform frequency dithering technique with 15 switching frequencies with 1 kHz frequency steps from 32−46 kHz having unequal persisting time or dithering duties for each of the selected switching frequencies. This paper also focuses on the sidebands produced due to frequency dithering, and the effective noise reduction is calculated with an RBW of 9 kHz, considering the noise floor, which has been largely neglected in the literature. The proposed technique achieves a significant noise reduction of 10dBµV over the conducted EMI zone as compared to single-frequency operation. The experimental validations are performed on a 1 kW SiC MOSFET-based DC-DC buck converter prototype.

Load-commutated inverter-based topologies are popularly used in high-power drive applications mainly due to the advantages offered by the thyristor such as high reliability, lesser losses, lower cost, and availability at high power levels. The LCI-fed drives suffer from the well-known disadvantage of low-frequency toque harmonics originating due to the quasi-square wave nature of machine current. These low-frequency oscillations are more critical at starting and low-speed operation of the drive, as they can excite mechanical resonance and cause permanent damage to the system. This paper proposes a selective harmonic minimization-based PWM method for a CSI fed multiphase induction machine drive which offers an improved torque profile during starting and low-speed operation. In the proposed topology, the MV-rated CSI operates in PWM mode and supplies all the power requirements of the machine. The CSI commutation is achieved by a low-voltage VSI without any additional complex commutation circuitry. The proposed topology is experimentally validated on a 37.5 kW multi-phase induction machine with 1.6 kV rated HV winding and 400 V rated auxiliary LV winding.

Series-connection of SiC MOSFET is a viable solution for realizing medium voltage power converters(2-15 KV). Active gate driving techniques further improve these converters' efficiency and power density. A significant challenge in the series connection of SiC MOSFET is voltage imbalance during turn-off. This paper discusses the voltage imbalance issue during series connected body diode turn-off instants due to parasitic capacitance. An active control technique for voltage balancing is proposed by partially turning ON MOSFET which shares higher voltage, using controlled gate current injection. The proposed voltage balancing control technique is experimentally validated in a double pulse test setup using two series connected CREE 1.2 KV, 33A SiC MOSFETs at a dc bus voltage of 800V.

Single-Phase Induction Motors (SPIMs) have dominated the ceiling fan industry for many years. Recently Permanent Magnet Brushless Direct Current (PMBLDC) Motors took over the market owing to their low power consumption for the same air delivery as SPIMs, complying with the Bureau of Energy Efficiency (BEE) regulations. Despite having simple, rugged, low cost and maintenance-friendly properties, three-phase induction motor (IM) has never been used in ceiling fan applications. This paper presents design procedures to maximise the efficiency of IM -based ceiling fan motors mostly by optimal magnetic material usage. IM provides better efficiency than SPIM and a better cost profile than PMBLDC motors with the same power input. The improved efficiency is achieved by the effective usage of the magnetic circuit, proper copper utilisation, and proper selection of pole numbers. All the designs in this paper are validated by Finite Element Method Magnetics (FEMM), an open-source finite element analysis (FEA) software. Also, the designed IM-based ceiling fan motor is manufactured and tested successfully.

SiC MOSFETs have the ability to switch within few tens of nanoseconds (<;50ns). But when switched with full speed under moderate amount of parasitic inductance(100nH-150nH), it exhibits a large ringing for few hundreds of nano seconds. Present paper proposes a novel, simple, low cost active gate driver to address this issue. The present work involves the design of a digital gate driver using a self commutating switch, which turns off by itself when the set gate charge to the device is delivered. The proposed method is simple and very effective to dampen out the oscillation in the device. The proposed gate driver is implemented in double pulse hardware test set up with 1.2kV, 36A Cree SiC MOSFET (C2M0080120D).

The back-emf based sensorless vector control method for a surface mount permanent magnet synchronous motor (SMPMSM)provides sufficiently good performance in medium and high speed range with simple control structure. Since back-emf based sensorless control is ineffective in low speed range, I-f open loop method is used for starting and a change over to sensorless control is performed. However, loss of synchronism may occur if the frequency ramp rate of I-f control is chosen arbitrarily. In this paper, a controller is proposed to dynamically adjust the slope of frequency ramp in the ramp-up interval, which works in conjunction with the conventional I-f control. The controller controls the total torque demand below the torque capability of the motor by adjusting the frequency slope. To overcome the inherent mid-frequency instability of I-f control, a reference speed modulator is included in the control. Stable starting of a 25kW PMSM drive with I-f control using the proposed method is validated with experimental results.

A high power Y : Y/Δ three-phase Dual Active Bridge (DAB) topology offers higher power density, smaller switching stress, smaller volume of magnetics and smaller DC capacitor over single phase DAB. Therefore this topology is suitable for medium voltage (MV) applications. The high-frequency DAB currents are nearly sinusoidal suited for D-Q transformation which enables fast average mode current control for device protection. But it requires fast ADC conversions and processing speed to implement this control. Also the PWM channel requirement for this topology is high. A DSP repeats an infinite loop of calculations serially. Thus it has limited loop speed in case of longer algorithm size which limits the control bandwidth. An FPGA based control is suitable as it can process the algorithm in programmable combinational logic circuits which offer few nano-seconds of propagation delay. And thus the only speed limitation is the ADC conversion speed. But an FPGA board does not readily offer all the features required for this application. Therefore an ultra-fast 2 MSPS parallel ADC interface board has been developed to achieve the control objectives for the topology in this paper.