Demo Data from EDBT 2026 / reviewers in the wild / expert
Yu-Hua Wu
dblp:123/5693
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2013
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.2 | 1 | 2013 | Counter-Based Output Selection for Test Response Compaction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013 |
Electronic design automation › hardware verification and test
test response compaction |
0.2 | 1 | 2013 | Counter-Based Output Selection for Test Response Compaction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013 |
Methods — techniques the papers use, named apart from their topics
automatic test pattern generation · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2013 | Counter-Based Output Selection for Test Response CompactionabstractOutput selection is a recently proposed test response compaction method, where only a subset of output response bits is selected for observation. It can achieve zero aliasing, full X-tolerance, and high diagnosability. One critical issue for output selection is how to implement the selection hardware. In this paper, we present a counter-based output selection scheme that employs only a counter and a multiplexer, hence involving very small area overhead and simple test control. The proposed scheme is ATPG-independent and thus can easily be incorporated into a typical design flow. Two efficient output selection algorithms are presented to determine the desired output responses, one using a single counter operation for simpler test control and the other using more counter operations for achieving a better test-response reduction ratio. Experimental results show that for stuck-at faults in large ISCAS'89 and ITC'99 benchmark circuits, 48%~90% reduction ratios on test responses can be achieved with only one counter and one multiplexer employed. Even better results, i.e., 76%~95% reductions, can be obtained for transition faults. It is also shown that the diagnostic resolution of this method is almost the same as that achieved by observing all output responses. Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty, Yu-Hua Wu |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 5 |