Electrowetting-on-dielectric (EWOD) chips have emerged as popular actuators for droplet-based digital microfluidic biochips. The chip-level design of EWOD chips allows for the integration electrode addressing and wire routing, thus helping cope with the increasing complexity of biochemical assays. Furthermore, high-frequency EWODs also facilitate finishing time-sensitive bioassays such as incubation and emerging flash chemistry in specific time periods. However, the reliability of the EWOD chip is reduced by the contact angle change reduction problem as a result of the repeated and frequent switching of electrodes. Thus, the chip-level design of EWOD chips should consider reliability, electrode addressing, and the wire routing problem. This paper presents a graph-based chip-level design algorithm. By setting the switching-time constraint, the number of switching times can be limited to minimize the impact of the contact angle change reductions problem. Also, a progressive addressing and routing approach is proposed to overcome the complex wire routing problem. Experimental results show the proposed algorithm effectively minimizes the impact of the contact angle change reduction problem, thus providing a reliable chip-level design with a feasible wire routing solution with the required number of pins.

Nowadays, electrowetting-on-dielectric (EWOD) chips have become the most popular actuator for droplet-based digital microfluidic biochips. As the complexity of biochemical assay increases, the chip-level design of EWOD chips which integrates electrode addressing and wire routing are widely adopted. Furthermore, to finish many time-sensitive bioassays such as incubation and emerging flash chemistry in a specific time, a high-frequency EWOD is used to satisfy the demand. However, the reliability of the EWOD chip degrades due to the contact angle reduction problem incurred by huge number of switching times of an electrode. Thus, the reliability issue, electrode addressing, and wire routing problem should be considered together in the chip-level design of an EWOD chips. In this paper, a graph-based chip-level design algorithm is presented. By setting the switching-time constraint, the number of switching times can be limited to minimize the impact of contact angle reductions problem. Also, a progressive addressing and routing approach is proposed to overcome the challenge of complex wire routing problem. Experimental results show that the influence of contact angle reduction problem can be effectively minimized by proposed algorithm. A reliable chip-level design with feasible wire routing solution can be generated with number of pins are satisfied.

Electrowetting-on-dielectric (EWOD) chips have become the most promising technology to realize pin-constrained digital microfluidic biochips (PDMFBs). Reliability is a critical factor in the design flow of EWOD chips, it directly affects the execution of bioassays. The trapped charge problem is the major factor degrading chip reliability, and this problem is induced by excessive applied voltage. Nevertheless, to comply with the pin constraint for PDMFBs, signal merging is inevitably involved, and thereby incurring trapped charges due to unawareness of the applied voltage. Except for the trapped charge problem, the wire routing required to accomplish electrical connections increases the design complexity of pin-constrained EWOD chips. However, previous research has failed to address the problems of excessive applied voltage and wire routing. Therefore, the resulting chip is more likely to fail during execution or cannot be realized because of the wire routing problem. A network-flow-based algorithm for reliability-driven pin-constrained EWOD chips is presented in this paper. The proposed algorithm not only minimizes the reliability problem induced by signal merging, but also prevents the operational failure caused by inappropriate addressing results. The proposed algorithm also provides a comprehensive routing solution for EWOD chip-level designs. The experimental results demonstrate the effectiveness of the proposed algorithm on real-life chips.

Recently, digital microfluidic biochips (DMFBs) have revolutionized many biochemical laboratory procedures and received much attention due to their many advantages, such as high throughput, automatic control, and low cost. To meet the challenges of increasing design complexity, computer-aided-design (CAD) tools have been used to build DMFBs efficiently. Current CAD tools generally conduct a two-stage based design flow of fluidic-level synthesis followed by chip-level design to optimize fluidic behaviors and chip architecture separately. Nevertheless, existing fluidic-chip design gap will become even wider with a rapid escalation in the number of assay operations incorporated into a single DMFB. As more and more large-scale assay protocols are delivered in the current emerging marketplace, this problem may potentially restrict the effectiveness and feasibility of the entire DMFB realization and thus needs to be solved quickly. In this paper, we propose the first fluidic-chip co-design methodology for DMFBs to effectively bridge the fluidic-chip design gap. Our work provides a comprehensive integration throughout fluidic-operation scheduling, chip layout generation, control pin assignment, and wiring solution to achieve higher design performance and feasibility. Experimental results show the effectiveness, robustness, and scalability of our co-design methodology on a set of real-life assay applications.

Electrowetting-on-dielectric (EWOD) chips have become the most popular actuators, particularly for droplet-based digital microfluidic biochip (DMFB) systems. In order to enable the electrical manipulations, wire routing is a key problem in designing EWOD chips. Unlike traditional very-large-scale-integration (VLSI) routing problems, in addition to routing-path establishment on signal pins, the pin-constrained EWOD-chip routing problem must address the issue of signal sharing for pin-count reduction under a practical constraint posed by a limited pin-count supply. Moreover, EWOD-chip designs might incur several obstacles in the routing region due to embedded devices for specific fluidic protocols. However, no existing work considers the EWOD-chip routing with obstacles and, therefore, lots of manual design efforts are involved. To remedy this insufficiency, we propose in this paper the first routing algorithm for pin-constrained EWOD chips with obstacle avoidance. The proposed algorithm, based on effective integer-linear-programming (ILP) formulation as well as efficient routing framework, can achieve high routability with a low design complexity. Experimental results based on real-life chips with obstacles demonstrate the high routability of proposed algorithm for pin-constrained EWOD chips with obstacle avoidance.

Electrowetting-on-dielectric (EWOD) chips have become the most promising technology to realize pin-constrained digital microfluidic biochips (PDMFBs). In the design flow of EWOD chips, reliability is a critical challenge as it directly affects execution of bioassays. The major factor to degrade chip reliability is the trapped charge problem, which is induced by excessive applied voltage. Nevertheless, to comply with the pin constraint for PDMFBs, signal merging is inevitably involved, and thereby incurring trapped charges due to unawareness of applied voltage. Except for the trapped charge problem, wire routing to accomplish electrical connections increases the design complexity of pin-constrained EWOD chips. Unfortunately, no existing works tackle the problems of excessive applied voltage and wire routing, and thus the resultant chip will have more probabilities to fail during execution or can not be realized because of wire routing problem. In this paper, we present a network-flow based algorithm for reliability-driven pin-constrained EWOD chips with the consideration of voltage issue. Our algorithm not only minimizes the reliability problem induced by signal merging but also provides a comprehensive routing solution for EWOD chip-level designs. The experimental results demonstrate the effectiveness of proposed algorithm on real-life chips.