Abstract The sixth-generation (6G) mobile network implements the social vision of digital twins and ubiquitous intelligence. Contrary to the fifth-generation (5G) mobile network that focuses only on communications, 6G mobile networks must natively support new capabilities such as sensing, computing, artificial intelligence (AI), big data, and security while facilitating Everything as a Service. Although 5G mobile network deployment has demonstrated that network automation and intelligence can simplify network operation and maintenance (O&M), the addition of external functionalities has resulted in low service efficiency and high operational costs. In this study, a technology framework for a 6G autonomous radio access network (RAN) is proposed to achieve a high-level network autonomy that embraces the design of native cloud, native AI, and network digital twin (NDT). First, a service-based architecture is proposed to re-architect the protocol stack of RAN, which flexibly orchestrates the services and functions on demand as well as customizes them into cloud-native services. Second, a native AI framework is structured to provide AI support for the diverse use cases of network O&M by orchestrating communications, AI models, data, and computing power demanded by AI use cases. Third, a digital twin network is developed as a virtual environment for the training, pre-validation, and tuning of AI algorithms and neural networks, avoiding possible unexpected losses of the network O&M caused by AI applications. The combination of native AI and NDT can facilitate network autonomy by building closed-loop management and optimization for RAN.

Recently, the edge-device DNN training has become of high importance, while the computation and access energy consumption of are too large. This paper proposes a CPE (Compress Process Element) with three characteristics. Firstly, CPE has a method of Reordering and Reusing Data (RRD) by controlling the output to reorder data. Secondly, CPE owns a Multi-directional Redundant Skip (MRS) mechanism, which anticipates all zeros and duplicate fields in advance. Thirdly, CPE contains a scheme to transform The Calculation Format (TCF), which transforms the input into another form. Evaluated with 28nm CMOS process, using CPE achieves 2.02 × energy reduction and offer 1.73 × speed up outperforming state-of-the-art trainable processor GANPU.

Coarse-Grained Reconfigurable Architecture (CGRA), especially the one with multiple parallelized Processing Element Arrays (PEA), possesses flexible programmability and high parallel computational efficiency, which relies upon an efficient memory architecture to deliver the corresponding computing power. Multi-PEA oriented CGRA allows for mapping various applications and thus demands a flexible memory to adapt to the ever-changing workloads, whose parallel access also requires an efficient multi-port memory. However, the existing memory designs for CGRA are hard to satisfy those requirements since conventional rigid memories fail to provide the desired flexibility due to fixed structure, and traditional multi-port designs are impractical due to large overhead. Therefore, this paper proposes a hardware/software (HW/SW) hybrid reconfigurable multi-port memory architecture (RMP-MEM) with an instructive analysis for the multi-PEA oriented CGRA. RMP-MEM supports adaptive memory partition and programmer-defined access modes to adapt the different features of memory accesses. Also, RMP-MEM achieves an efficient multi-port implementation by a partially shared mechanism. Furthermore, the microarchitecture of RMP-MEM is optimized multi-directionally, resulting in a significant performance gain. The experimental results indicate that RMP-MEM reduces the parallel access latency by 81.1% and exhibits 28.3% energy efficiency improvement compared to prior designs.

Spatial architecture is a high-performance architecture that uses control flow graphs and data flow graphs as the computational model and producer/consumer models as the execution models. However, existing spatial architectures suffer from control flow handling challenges. Upon categorizing their PE execution models, we find that they lack autonomous, peer-to-peer, and temporally loosely-coupled control flow handling capability. This leads to limited performance in intensive control programs.

Coarse-Grained Reconfigurable Architecture (CGRA) is a high-performance computing architecture. However, existing CGRA silicon utilization is low due to the lack of fine-grained parallelism inside Processing Element (PE) and general coarse-grained parallel approach on PE array. No fine-grained parallelism in PE not only leads to low silicon utilization of PE, but also makes the mapping loose and irregular. No generalized parallel method for the mapping cause low PE utilization on CGRA. Our goal is to design an execution model and a Mixed-granularity Parallel CGRA (MP-CGRA), which is capable to fine-grained parallelize operators excution in PEs and parallelize data transmission in channels, leading to a compact mapping. A coarse-grained general parallel method is proposed to vectorize the compact mapping. Evaluated with Machsuite, MP-CGRA achieves an improvement of 104.65% silicon utilization on PE array and a 91.40% performance per area improvement compared with baseline-CGRA.

Coarse-grained reconfigurable architecture (CGRA) is an emerging hardware architecture, with reconfigurable Processing Elements (PEs) for executing operations efficiently and flexibly. One major challenge for current CGRA compilers is the scalability issue for large loop applications, where valid loop mapping results cannot be obtained in an acceptable time. This paper proposes an enhanced loop mapping method based on Graph Neural Network (GNN), which effectively addresses the scalability issue and generates valid loop mapping results for large applications. Experimental results show that the proposed method enhances the compilation time by 10.8x on average over existing methods, with even better loop mapping solutions.

Visible light communication on the basis of IM/DD system has attracted enormous interest in recent years. One of the major topics to be investigated in this field is orthogonal frequency division multiplexing (OFDM). This paper proposed a novel iterative receiver for PAM-DMT based hybrid OFDM in order to enhance its performance. The concept of OFDM models and structure of conventional receiver are introduced firstly. Then the proposed iterative receiver and its computational complexity are presented. Simulation showed that under the same bit error rate (BER) of 10−4, the required signal to noise ratio (SNR) for transmitting has been reduced for about 2.5 dB. In conclusion, the proposed iterative receiver could achieve a considerable performance gain under a variety of simulation conditions, which demonstrated its potential for being applied in the visual light communication system.

A pixelated MIMO wireless optical communication system is introduced, which transmits a series of time-varying coded images that can be received and decoded by commercial digital cameras. The system exploits the bokeh effect to obtain fixed-scale images at all link distances by placing a convex lens in front of the transmitter array at its focal length and focusing the receiver at infinity. This spatial-angular mapping simplifies the receiver structure requiring no re-focusing as the receiver moves. As an additional benefit, this mapping can also be exploited to provide location information to the receiver. The channel model is measured and modeled and rateless codes are applied to track the truncation of receive images for various link ranges and angular offsets. A proof-of-concept optical communication system is implemented with an LCD display and a high-speed CMOS camera.