A novel single-ended variable gain power amplifier (VGPA) topology, named as shunt Common Source-Common Gate VGA, is introduced in this article. A fundamental building block as CS-CG Unit (SGU) is proposed to provide gain tuning function with a sufficient dynamic range. Some valuable characteristics of a single unit are elaborated and then utilized to finally compose a VGPA for compact 5G phased array applications. A prototype VGPA is taped out in commercial 65nm CMOS process as an experimental verification of such theory. Satisfying measurement results are obtained with an absolute bandwidth ranging from 22.6 to 37GHz (fractionally 48.3%) and a gain dynamic range of 12.8dB among which phase variation remains less than 4.8°. Furthermore, the output 1-dB compression point is measured to be around 12dBm at several in-band frequencies. Benefiting from the full single-ended configuration, the footprint shrinks to a large extent as the circuit occupies only 0.11mm2.

Here, we present a millimeter-wave (mm-Wave) broadband power amplifier (PA) with a common-mode (CM) stability improvement technique. Unlike conventional broadband PAs, which consider only the differential-mode (DM) stability, our proposed PA simultaneously enhances the DM stability and the CM stability. To ensure CM stability, a small resistor is first connected in series to a capacitor to reduce its Q factor; then, these components are attached in parallel at the center tap of the input balun to increase the CM path loss. Therefore, the stabilization of the PA can be improved over the entire frequency band to ensure a properly broadband work. Our proposed broadband PA with CM stability enhancement technique is finished in a commercial 65 nm CMOS process with a core area of 0.13 mm2. Adopting continuous-wave testing, the PA exhibits 56.3% 1-dB output 1-dB compression point power (OP1dB) fractional bandwidth and 3-dB small signal gain fractional bandwidth from 23 to 41 GHz that covers the whole Ka-band. At 28/39 GHz, the PA provides +14.8-/+14.1-dBm saturation output power (Psat), +12.4-/+12.0-dBmOP1dBand 29.8%/23.8% peak power added efficiency (PAE). The measured stability parameters indicate the proposed CM stability enhanced broadband PA is unconditionally stable over the entire frequency band. For a 100-MHz 1-CC 64-QAM signals (roll-off factor = 0.45 and PAPR = 7.1 dB), at a carrier frequency of 28 GHz, the PA demonstrates 8.6 dBm average output power (Pavg), 5% average power added efficiency (PAEavg), -32.4 dBc adjacent channel leakage ratio (ACLR) and -25.4 dB EVM. For a 400-MHz single-carrier 64-QAM signal, this proposed PA still provides 8.1-dBmPavgand 4.5%PAEavgwith a -34.2 dBc ACLR and -25.3 dB rms EVM at 28 GHz.

This paper presents a fast transient response capless low-dropout (LDO) regulator in 65 nm CMOS process for system-on-chip (SOC). The LDO regulator utilizes a feedforward ripple cancellation circuit (FFRCC) to achieve high power supply rejection (PSR), and a voltage damper is used to enhance transient response. Besides, a negative capacitance circuit (NCC) is added to the gate of the power stage to expand the bandwidth of FFRCC. The proposed LDO regulator is fabricated in 65 nm CMOS technology. Its voltage recovery time is 1.1 μs and 400 ns, respectively, when the load current steps from 200 μA to 50 mA or 50 mA to 200 μA with the rise/fall time of 100 ns. Its overshoot and undershoot voltages are 114 mV and 98 mV, respectively. Moreover, the regulator achieves -78 dB PSR at 2 MHz.

This article presents a dual-band receiver front-end based on a reconfigurable Hartley architecture with double frequency conversion for millimeter-wave wireless communication. By controlling working states of band-select switches, the receiver is able to reach different RF bands without increasing or altering local-oscillator (LO) and intermediate-frequency bands. To reduce power consumption and save chip area, RF quadrature mixers are co-designed with the last stage of a dual-band low-noise amplifier and reuse its dc current. In addition, a self-mixing frequency tripler with a transformer-based compact hybrid is developed to multiply an input LO and provide quadrature LO signals for the RF mixers. The prototype receiver is demonstrated in a 65 nm CMOS process. Measurement results show that the receiver successfully covers two frequency bands of 24.6~28 GHz and 55.6~60 GHz, and the corresponding peak conversion gains are up to 24.5 dB and 26.3 dB, respectively. In these two bands, the minimum single-sideband noise figures are 7.5 and 7.8 dB. The tested image-rejection ratio of the dual-band receiver is better than 30 dB in both 26.5~30.0 GHz and 57.5~60.5 GHz bands. Besides, the receiver also demonstrates its capability of supporting up to 256QAM modulation and 3.2-Gb/s data-rate transmission.

This article presents an 18~30 GHz vector-sum phase shifter for wireless application in the millimeter-wave regime. It is composed of an I/Q signal generator, two variable-gain amplifiers (VGA), and a digital-to-analog converter with a quadrant selector. To attain wideband quadrature signal, a two-stage hybrid based on transformers is proposed to realize the I/Q signal generator. The first- and second-stage hybrids are designed with different resonating frequencies. As a result, the amplitude and phase errors of the I/Q signal generator are significantly decreased in a wide frequency band. In addition, theoretical analysis based on a simplified equivalent-circuit model is performed to guide the circuit implementation, and its correctness is demonstrated by electromagnetic simulation. To mitigate the impact of the VGAs’ parasitics on the phase performance, a capacitive-neutralization technique is applied to cancel parasitics of transistors in the VGAs. A prototype circuit is designed using a 130-nm SiGe BiCMOS process. The measured results show that the circuit achieves a root-mean-square (RMS) amplitude error of less than 1.4 dB and an RMS phase error of 1.4°~3.4° across 18~32 GHz. The tested peak gains of all the phase states are −1~4.5 dB with an input balun ($\approx 1.9$dB loss) and an output balun ($\approx 2$dB loss) at 22 GHz. Also, the input 1-dB compression point and noise figure are tested, which are$\geq $-1 dBm and$\leq 15.5$dB in the targeting frequency band.

This paper presents a 5-bit dual-band active phase shifter for both 28-GHz and 60-GHz phased array applications. With the inclusion of a dual-band hybrid transformer-based quadrature generator and a wide-band vector modulator, this phase shifter achieves 3-dB gain bandwidth of 27-34 GHz and 55-63 GHz. The vector modulator is composed of a balun-loaded buffer and a Gilbert cell-based variable gain amplifier (VGA). Further, a digital-to-analog convertor (DAC) controls the gain of vector modulator to achieve 5-bit phase resolution. The circuit is designed in a 65-nm CMOS technology. Post layout simulation results show that the RMS phase error is 2.27° ~ 2.94° and 1.96° ~ 3.07° and the RMS gain error is 1.17 ~ 1.53dB and 1.26 ~ 1.91dB in the 3-dB bandwidths of 27-34 GHz and 55-63 GHz, respectively. The post-layout simulated input-referred 1-dB compression point (IP1dB) is larger than −8.7dBm, while the peak gain is −0.17dB at 29 GHz with an average power consumption of all phase states of 32.4 mW. The core area of the phase shifter is 560 $\mu m\times 560 \mu$m.

This paper presents a high-flexibility and low-cost transceiver (TRX) in 65-nm CMOS process for fifth-generation (5G) communications. The TRX is based on local-oscillator (LO) phase-shifting architecture with 5 bits of gain control and 6 bits of phase control. To enhance the transceiver gain, bandwidth, efficiency, noise performance, and achieve ultra-low amplitude and phase errors without any calibration, a variety of innovative techniques are introduced in this work. The TX path demonstrates a measured peak conversion gain (CG) of 43.1 dB with the IF fractional bandwidth of 79% from 3.5 to 8.1 GHz and the RF of20% from 23.4 to 28.5 GHz. The measured TX OP1dB is up to 13.3 dBm at26 GHz. In the RX mode, the measured peak CG is 29.6 dB with 134% fractional bandwidth of the IF (2.1 to 10.6 GHz), 19% of the RF (23.7 to 28.6 GHz) and the minimum noise Figure is 5.5 dB (including T/R switch). Moreover, the TRX with 6-bit phase resolution realizes a measured RMS amplitude and phase errors of less than 0.63 dB and 2. 4°, respectively. The proposed wideband transceiver simultaneously implements broadband RF/LO/IF while maintaining ultra-low gain and phase errors without any calibration. Such a system with only one chip can meet the requirements of IF, LO and RE frequency combinations of different scenarios, which is suitable for high data-rate and low cost 5G applications.

A wideband CMOS low-noise amplifier (LNA) with multiple resonant frequencies is demonstrated in this article. A common source (CS) with inductive degeneration topology is widely employed in LNA circuit design to decouple the input impedance from the noise figure (NF). Since CS with inductive degeneration topology only achieves a single resonant frequency, it generally has narrow bandwidth performance. Through impedance transformation analysis of the matching circuit, a shunt resonator combined with inductive degeneration topology employed for input impedance transformation is carefully constructed to form multiple resonant frequencies. By placing resonant frequencies further apart from each other, impedance fluctuations within a wideband frequency range can be alleviated. In addition, the noise performance of this topology is the same as that of a conventional CS source-degenerated structure. The proposed LNA for the whole K/Ka Band is implemented in a commercial 65-nm CMOS process. It occupies 0.28 mm2. Under a 1.0 V voltage supply, the LNA achieves 3-dB gain bandwidth of 28 GHz from 16.5 GHz to 44.5 GHz. Within the whole 3-dB bandwidth, the gain is larger than 15.5 dB, the NF is less than 4.8 dB with a minimal value of 2.72 dB, and the input 1-dB gain compression point (IP1dB) varies from −24 dBm to −12 dBm.

In this article, a CMOSKu-band phased-array transmitter with eight elements is demonstrated. To mitigate the measurement time and complexity, a built-in self-test (BIST) circuit is developed in this chip. A fully symmetrical sampling structure is proposed to improve the testing accuracy of the BIST system. To decrease the phase and amplitude errors, two compensation methods based on inductors and capacitors are, respectively, used in the phase shifters and attenuators to minimize severe parasitic effects of transistors in high-frequency bands. In addition, a scalable power divider is developed to save chip area and reduce insertion loss. According to the measurement results, the 5-bit passive phase shifter in each transmitting channel achieves less than 3.6° root-mean-square phase error (RMSPE) and 0.8-dB root-mean-square amplitude error (RMSAE). The transmitter’s attenuators are formed by four bridge-$T/\pi $-type units and achieve less than 0.94-dB RMSAE and RMSPE of 3.2°. Each channel of the transmitter is capable of delivering about 13-dBm linear power at 16 GHz. The BIST system is also employed to detect the phase and amplitude performances of the eight-element transmitter, and the BIST testing errors are less than 10.3% compared to the microwave equipment measurement.

A 5-bit active digital step attenuator (DSA), which simultaneously achieves low amplitude and phase variations, is proposed for wideband phased-array applications. The input and output impedances for each attenuation unit under the reference state and the attenuation state can remain basically the same. Therefore, the amplitude and phase errors caused by a load impedance mismatch between each unit can be alleviated. Implemented in 130-nm silicon-germanium (SiGe) BiCMOS technology platform, the proposed DSA provides a maximum attenuation range of 15.5 dB with 0.5-dB steps. It exhibits an insertion loss (IL) less than 13 dB and input/output return losses less than -10 dB from 31 to 41 GHz. In addition, with the help of minimized amplitude and phase variations, the DSA exhibits a root-mean-square (rms) amplitude error less than 0.2 dB and an rms phase error less than 2.5° at 33-41 GHz, which are the lowest such errors ever reported. The chip core area of the DSA is 0.22 mm2(0.5 mm × 0.44 mm). It shows a suitable performance for 5G applications.