Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data.

Yun Heo

dblp:123/7612 · DBLP profile ↗
← Back
6ranked-venue papers
2as first author
1since 2021 · last 2023
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 3 · 2 first-authorSoftware engineering, systems software and programming languages · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 64% Integrated circuit design · 32% Parallel and multicore computing · 4%
Interdisciplinary, comprehensive, and emerging computing
2 papers
Bioinformatics and computational biology · 100%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › placement › circuit placement
3D IC placement
0.712023
Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Integrated circuit design
heterogeneous integration
0.712023
Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Electronic design automation
physical design
0.712023
Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Bioinformatics and computational biology › sequence analysis
error correction
0.422016
BLESS 2: accurate, memory-efficient and fast error correction method · Bioinform. 2016
BLESS: Bloom filter-based error correction solution for high-throughput sequencing reads · Bioinform. 2014
Bioinformatics and computational biology › sequence analysis
sequencing data analysis
0.422016
BLESS 2: accurate, memory-efficient and fast error correction method · Bioinform. 2016
BLESS: Bloom filter-based error correction solution for high-throughput sequencing reads · Bioinform. 2014
Parallel and multicore computing › parallel programming models › hybrid programming models
hybrid MPI/OpenMP
0.112016
BLESS 2: accurate, memory-efficient and fast error correction method · Bioinform. 2016
Bioinformatics and computational biology
next-generation sequencing
0.112014
BLESS: Bloom filter-based error correction solution for high-throughput sequencing reads · Bioinform. 2014

Methods — techniques the papers use, named apart from their topics

bloom filter · 0.7tier partitioning · 0.7constrained placement · 0.7OpenMP · 0.5MPI · 0.5
YearPublicationVenuePosition
2023 Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs
abstract
3-D integration technology is one of the leading options to advance Moore’s Law beyond conventional scaling. One of the 3-D integration choice is the heterogeneous integration with the benefits of power saving over the homogeneous integration. With the lack of commercial 3-D tools, existing 3-D physical design flows utilize 2-D commercial tools to perform 3-D integrated circuit (3-D IC) physical synthesis. Specifically, these flows build 2-D designs first and then convert them into 3-D designs. However, several works demonstrate that design qualities degrade during this 2-D–3-D transformation and some of the flows do not support heterogeneous integration. In this article, we propose Snap-3D, a constraint-driven placement approach to build commercial-quality 3-D ICs, which supports both homogeneous and heterogeneous 3-D ICs. Our key idea is based on the observation that if the standard cell height is contracted and partitioned into multiple tiers, any commercial 2-D placer can place them onto the row structure and naturally achieve high-quality 3-D placement. This methodology is shown to optimize power, performance, and area (PPA) metrics across different tiers simultaneously and minimize the aforementioned design quality loss. Experimental results on seven industrial designs demonstrate that Snap-3D achieves up to 10.9% wirelength, 9% power, and 25% performance improvements compared with state-of-the-art 3-D design flows.
Pruek Vanna-Iampikul, Chengjia Shao, Yi-Chen Lu, Sai Pentapati, Yun Heo, Jae-Seung Choi, Sung Kyu Lim
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.5
2020 A Method of Via Variation Induced Delay Computation
abstract
As process technologies are scaled down, interconnect delay becomes major component of entire path delay, and vias represent a significant portion of the interconnect delay. In this paper, a novel variation-aware delay computation method for vias is proposed. Our experiments show that this method can reduce over five percent of pessimism in arrival time calculation when it is compared with state-of-the-art solutions.
Moonsu Kim, Yun Heo, Seungjae Jung, Kelvin Le, Nathaniel Conos, Hanif Fatemi, Jongpil Lee, Youngmin Shin
DATE2
2016 BLESS 2: accurate, memory-efficient and fast error correction method
abstract
UNLABELLED: The most important features of error correction tools for sequencing data are accuracy, memory efficiency and fast runtime. The previous version of BLESS was highly memory-efficient and accurate, but it was too slow to handle reads from large genomes. We have developed a new version of BLESS to improve runtime and accuracy while maintaining a small memory usage. The new version, called BLESS 2, has an error correction algorithm that is more accurate than BLESS, and the algorithm has been parallelized using hybrid MPI and OpenMP programming. BLESS 2 was compared with five top-performing tools, and it was found to be the fastest when it was executed on two computing nodes using MPI, with each node containing twelve cores. Also, BLESS 2 showed at least 11% higher gain while retaining the memory efficiency of the previous version for large genomes. AVAILABILITY AND IMPLEMENTATION: Freely available at https://sourceforge.net/projects/bless-ec CONTACT: [email protected] SUPPLEMENTARY INFORMATION: Supplementary data are available at Bioinformatics online.
Yun Heo, Anand Ramachandran 0001, Wen-Mei W. Hwu, Jian Ma 0004, Deming Chen
Bioinform.1
2015 FPGA accelerated DNA error correction
Anand Ramachandran 0001, Yun Heo, Wen-Mei W. Hwu, Jian Ma 0004, Deming Chen
DATE2
2014 BLESS: Bloom filter-based error correction solution for high-throughput sequencing reads
abstract
MOTIVATION: Rapid advances in next-generation sequencing (NGS) technology have led to exponential increase in the amount of genomic information. However, NGS reads contain far more errors than data from traditional sequencing methods, and downstream genomic analysis results can be improved by correcting the errors. Unfortunately, all the previous error correction methods required a large amount of memory, making it unsuitable to process reads from large genomes with commodity computers. RESULTS: We present a novel algorithm that produces accurate correction results with much less memory compared with previous solutions. The algorithm, named BLoom-filter-based Error correction Solution for high-throughput Sequencing reads (BLESS), uses a single minimum-sized Bloom filter, and is also able to tolerate a higher false-positive rate, thus allowing us to correct errors with a 40× memory usage reduction on average compared with previous methods. Meanwhile, BLESS can extend reads like DNA assemblers to correct errors at the end of reads. Evaluations using real and simulated reads showed that BLESS could generate more accurate results than existing solutions. After errors were corrected using BLESS, 69% of initially unaligned reads could be aligned correctly. Additionally, de novo assembly results became 50% longer with 66% fewer assembly errors. AVAILABILITY AND IMPLEMENTATION: Freely available at http://sourceforge.net/p/bless-ec CONTACT: [email protected] SUPPLEMENTARY INFORMATION: Supplementary data are available at Bioinformatics online.
Yun Heo, Deming Chen, Jian Ma 0004, Wen-Mei W. Hwu
Bioinform.1
2012 TIGER: tiled iterative genome assembler
abstract
BACKGROUND: With the cost reduction of the next-generation sequencing (NGS) technologies, genomics has provided us with an unprecedented opportunity to understand fundamental questions in biology and elucidate human diseases. De novo genome assembly is one of the most important steps to reconstruct the sequenced genome. However, most de novo assemblers require enormous amount of computational resource, which is not accessible for most research groups and medical personnel. RESULTS: We have developed a novel de novo assembly framework, called Tiger, which adapts to available computing resources by iteratively decomposing the assembly problem into sub-problems. Our method is also flexible to embed different assemblers for various types of target genomes. Using the sequence data from a human chromosome, our results show that Tiger can achieve much better NG50s, better genome coverage, and slightly higher errors, as compared to Velvet and SOAPdenovo, using modest amount of memory that are available in commodity computers today. CONCLUSIONS: Most state-of-the-art assemblers that can achieve relatively high assembly quality need excessive amount of computing resource (in particular, memory) that is not available to most researchers to achieve high quality results. Tiger provides the only known viable path to utilize NGS de novo assemblers that require more memory than that is present in available computers. Evaluation results demonstrate the feasibility of getting better quality results with low memory footprint and the scalability of using distributed commodity computers.
Yun Heo, Izzat El Hajj, Wen-Mei W. Hwu, Deming Chen, Jian Ma 0004
BMC Bioinform.2