Deep neural networks (DNN) have become a significant applications in both cloud-server and edge devices. Meanwhile, the growing number of DNNs on those platforms raises the need to execute multiple DNNs on the same device. This paper proposes a dynamic partitioning algorithm to perform concurrent processing of multiple DNNs on asystolic-array-based accelerator. Sharing an accelerator's storage and processing resources across multiple DNNs increases resource utilization and reduces computation time and energy consumption. To this end, we propose a partitioned weight stationary dataflow with a minor modification in the logic of the processing element. We evaluate the energy consumption and computation time with both heavy and light workloads. Simulation results show a 35% and 62% improvement in energy consumption and 56% and 44% in computation time under heavy and light workloads, respectively, compared with single tenancy.

In the world of the Internet of Things (IoT), wireless sensor networks (WSNs) are an impressive technology. These networks are extremely resource constrained and require the design of energy-efficient routing techniques. The clustering and location prediction routing method based on multiple mobile sinks (CLRP-MMSs) for the Mobile Internet of Things (MIoT) is presented in this article. Recently, mobile sinks are used in routing more durability and energy saving in WSN. In this work, first, the entire nodes are divided into clusters, and then each cluster selects a cluster head (CH) by calculating the CH choosing function (CHCF). When clustering runs on networks with moving nodes, the possibility of disconnecting the nodes from CH nodes will cause a lot of data loss. It will change the amount of energy and rate of data received, but the amount of wasted energy is reduced by predicting the location and reducing the sink and CH nodes' distance. The simulation results using NS-2 clearly showed that the proposed method improves energy consumption at least 28.12% and increases throughput at least 26.74% compared to energy efficient routing algorithm with mobile sink support and high-available and location-predictive data gathering scheme using mobile sink methods.

Today's, a promising solution, namely wireless network‐on‐chip (WiNoC) is utilized in multi‐core systems to overcome the constraints of conventional on‐chip networks. In WiNoC architectures, wireless routers (WRs) provide high capacity wireless links to reduce the latency of multi‐hop communications. However, the buffer size of the WR antenna is limited, and under heavy traffic loads, it's filled and congestion occurs. On the other hand, network performance is degraded severely in the presence of head‐of‐line (HOL) blocking. Therefore, flow control and scheduling mechanisms are vital for improving the performance of WiNoCs. In this study, a flow control scheme based on an active queue management algorithm, and a priority‐based scheduling strategy are suggested. The proposed mechanisms are evaluated under uniform and Bit‐complement traffic patterns with different packet injection rate. The simulation results show that the proposed schemes have a significant impact on performance parameters, such as latency and throughput. Moreover, the saturation packet injection rate in WiNoC with four WRs is improved to about 33% under uniform traffic and is increased up to about 50% under the Bit‐complement traffic pattern. This is increased by 16 and 50% in WiNoC with 16 WRs for uniform and Bit‐complement traffic patterns, respectively, compared to the conventional WiNoCs.

In recent years, peer‐to‐peer (P2P) live streaming is popularised by the scalability and cost‐effectiveness of P2P networks. User satisfaction in P2P live streaming systems depends on several factors, including chunk scheduling techniques and overlay construction mechanisms in these systems. P2P live streaming systems are involved with the peer and chunk selection problems to improve quality parameters of streaming, such as playback continuity, startup delay, and playback latency. In this study, WidePLive as a P2P live video streaming system is proposed. In WidePLive, the authors proposed a low‐delay overlay construction mechanism and a mixed strategy based chunk scheduling scheme which are coupled together by a contribution‐aware peer selection strategy as a coupling feature to improve the quality parameter. The proposed overlay construction mechanism allows new peers to have the opportunity to connect with previous peers near the server and forms a low‐depth and low‐delay overlay. The proposed chunk scheduling scheme uses the benefits of Rarest First and Greedy strategies to trade‐off between quality parameters. The evaluation of WidePLive simulation results demonstrates an acceptable improvement in streaming performance and shows that WidePLive has lower startup delay and playback latency and higher playback continuity compared to previous works.

The interaction between cores and memory blocks, in multiprocessor chips and smart systems, has always been a concern as it affects network latency, memory capacity, and power consumption. A new 2.5-dimensional architecture has been introduced in which the communication between the processing elements and the memory blocks is provided through a layer called the interposer. If the core wants to connect to another, it uses the top layer, and if it wants to interact with the memory blocks, it uses the interposer layer. In a case that coherence traffic at the processing layer increases to the extent that congestion occurs, a part of this traffic may be transferred to the interposer network under a mechanism called load balancing. When coherence traffic is moved to the interposer layer, as an alternative way, this may interfere with memory traffic. This paper introduces a mechanism in which the aforementioned interference may be avoided by defining two different virtual channels and using multiple links which specifically determines which memory block is going to be accessed. Our method is based on the destination address to recognize which channel and link should be selected while using the interposer layer. The simulation results show that the proposed mechanism has improved by 32% and 14% latency compared to the traditional load-balancing and unbalanced mechanisms, respectively.

Convolutional neural networks have been proposed as an approach for classifying data corresponding to labeled and unlabeled datasets. The fast-growing data empowers deep learning algorithms to achieve higher accuracy. Numerous trained models have been proposed, which involve complex algorithms and increasing network depth. The main challenges of implementing deep convolutional neural networks are high energy consumption, high on-chip and off-chip bandwidth requirements, and large memory footprint. Different types of on-chip communication networks and traffic distribution methods have been proposed to reduce memory access latency and energy consumption of data movement. This paper proposes a new traffic distribution mechanism on a mesh topology using distributer nodes by considering memory access mechanism in the AlexNet, VggNet, and GoogleNet trained models. We also propose a flow mapping method (FMM) based on dataflow stationary which reduces energy consumption by 8%.

Parallel hardware accelerators for large-scale neural networks typically consist of several processing nodes, arranged as a multi- or many-core system-on-chip, connected by a network-on-chip (NoC). Recent proposals also benefit from the emerging 3D memory-on-logic architectures to provide sufficient bandwidth for neural networks. Handling the heavy traffic between neurons and memory and also the multicast-based inter-neuron traffic, which often varies over time, is the most challenging design consideration for the networks-on-chip in such accelerators. To address these issues, a reconfigurable network-on-chip architecture for 3D memory-on-logic neural network accelerators is presented in this paper. The reconfigurable NoC can adapt its topology to the on-chip traffic patterns. It can be also configured as a tree-like structure to support multicast-based neuron-to-neuron and memory-to-neuron traffic of neural networks. The evaluation results show that the proposed architecture can better manage the multicast-based traffic of neural networks than some state-of-the-art topologies and considerably increase throughput and power efficiency.

As the number of on-chip processor cores increases, power-efficient solutions are sought for data communication between cores. TheHelix-hnon-blocking photonic switch is developed to improve physical-layer and network performance parameters for a wide range of silicon nano-photonic multicore interconnection topologies. Traffic benchmarks and practical case studies using a cycle-accurate simulation environment indicate significantly reduced insertion loss providing improved bandwidth density and scalability to manycore plurality. Improvements in system performance parameters are quantified for network bandwidth, transmission efficiency, and latency in popular photonic internconnection topologies, in comparison to previous switch designs. For instance, utilizing the Helix-h switch in a mesh topology, the bandwidth is increased by 112 percent compared to the previously highest performing switch design. Execution time and energy efficiency are improved by up to 92 and 99 percent, respectively, for representative multicore applications. Finally, the technique is generalized to a novel graph-theoretic method for articulating blocking conditions in photonic switches.

Researches demonstrate that overheating can raise the risk of failure in electrical chips. Also, increasing processing demand of applications increase the number of IPCores inside the chips and subsequently make them being tightly coupled, which in turn can intensify the thermal issues. In this paper we propose an application specific temperature-aware mapping algorithm which maps IPCores such that thermal correlation between them would be taken as minimum with considering the performance impact. Simulation results show that the average peak temperature is reduced while applying our mapping onto four application graphs. Moreover the communication cost and energy consumption are also reduced.