Demo Data from EDBT 2026 / reviewers in the wild / expert
Haris Isakovic
dblp:123/8074
· DBLP profile ↗
9ranked-venue papers
2as first author
3since 2021 · last 2024
0000-0002-9413-1815ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 2 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Artificial intelligence
1 paper |
Motion planning and robot control · 50% Reinforcement learning · 50% | |
| Theoretical computer science
1 paper |
Logic in computer science · 100% | |
| Software engineering, system software, and programming languages
1 paper |
Requirements engineering and software design · 100% | |
| Computer networks
1 paper |
Internet of things and sensor networks · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Machine learning › Reinforcement learning
reinforcement learning for control |
0.8 | 1 | 2024 | DeepRIoT: Continuous Integration and Deployment of Robotic-IoT Applications · DAC 2024 |
Robotics › Motion planning and robot control
robot control |
0.8 | 1 | 2024 | DeepRIoT: Continuous Integration and Deployment of Robotic-IoT Applications · DAC 2024 |
Requirements engineering and software design › formal specification
requirements formalization |
0.6 | 1 | 2022 | DeepSTL - From English Requirements to Signal Temporal Logic · ICSE 2022 |
Logic in computer science › temporal logic
signal temporal logic |
0.6 | 1 | 2022 | DeepSTL - From English Requirements to Signal Temporal Logic · ICSE 2022 |
Logic in computer science
temporal logic |
0.6 | 1 | 2022 | DeepSTL - From English Requirements to Signal Temporal Logic · ICSE 2022 |
Internet of things and sensor networks › cyber-physical systems
robotic-iot |
0.2 | 1 | 2024 | DeepRIoT: Continuous Integration and Deployment of Robotic-IoT Applications · DAC 2024 |
Methods — techniques the papers use, named apart from their topics
transfer learning · 1.5multi-objective RL · 1.5deep reinforcement learning · 1.5neural machine translation · 1.1deep learning · 1.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | DeepRIoT: Continuous Integration and Deployment of Robotic-IoT ApplicationsabstractWe present DeepRIoT, a continuous integration and continuous deployment (CI/CD) based architecture that accelerates the learning and deployment of a Robotic-IoT system trained from deep reinforcement learning (RL). We adopted a multi-stage approach that agilely trains a multi-objective RL controller in the simulator. We then collected traces from the real robot to optimize its plant model, and used transfer learning to adapt the controller to the updated model. We automated our framework through CI/CD pipelines, and finally, with low cost, succeeded in deploying our controller in a real F1tenth car that is able to reach the goal and avoid collision from a virtual car through mixed reality. Meixun Qu, Zlatan Tucakovic, Ezio Bartocci, Dejan Nickovic, Haris Isakovic, Radu Grosu |
DAC | 6 |
| 2022 | DeepSTL - From English Requirements to Signal Temporal LogicabstractFormal methods provide very powerful tools and techniques for the design and analysis of complex systems. Their practical application remains however limited, due to the widely accepted belief that formal methods require extensive expertise and a steep learning curve. Writing correct formal specifications in form of logical formulas is still considered to be a difficult and error prone task. Ezio Bartocci, Dejan Nickovic, Haris Isakovic, Radu Grosu |
ICSE | 4 |
| 2022 | Towards Adaptive Quality Assurance in Industrial ApplicationsabstractWe propose the AQUILA framework (Adaptive Quality Assurance in Industrial Applications), a concept for digitalization in Industry 4.0 to support the entire industrial manufacturing chain, laying the groundwork for adaptive quality assurance in times of disrupted supply chains and, due to the COVID-19 pandemic, restricted travel possibilities. To that end, our proposed framework allows for the definition and description of industrial processes, quality assurance and testing protocols, and training scenarios in a comprehensive notation based on BPMN, and supports users in task execution, documentation, and evaluation by providing smart glass-based HCI with eye tracking technology, delivering a combination of process documentation, context-sensitive AR visualization, gaze-based interaction schemes, and remote maintenance and assistance functionality. Christian Thomay, Ulf Bodin, Haris Isakovic, Rainer Lasch, Nicholas J. P. Race, Christoph Schmittner, Germar Schneider, Zsolt Szepessy, Markus Tauber |
NOMS | 3 |
| 2019 | Sensyml: Simulation Environment for large-scale IoT ApplicationsabstractIoT systems are becoming an increasingly important component of the civil and industrial infrastructure. With the growth of these IoT ecosystems, their complexity is also growing exponentially. In this paper we explore the problem of testing and evaluating large scale IoT systems at design time. To this end we employ simulated sensors with the physical and geographical characteristics of real sensors. Moreover, we propose Sensyml, a simulation environment that is capable of generating big data from cyber-physical models and real-world data. To the best of our knowledge it is the first approach to use a hybrid integration of real and simulated sensor data, that is also capable of being integrated into existing IoT systems. Sensyml is a cloud based Infrastructure-as-a-Service (IaaS) system that enables users to test both functionality and scalability of their IoT applications. Haris Isakovic, Vanja Bisanovic, Bernhard Wally, Thomas Rausch, Denise Ratasich, Schahram Dustdar, Gerti Kappel, Radu Grosu |
IECON | 1 |
| 2017 | A Self-Healing Framework for Building Resilient Cyber-Physical SystemsabstractSelf-healing is an increasingly popular approach to ensure resiliency, that is, a proper adaptation to failures and attacks, in cyber-physical systems (CPS). A very promising way of achieving self-healing is through structural adaptation (SHSA), by adding and removing components, or even by changing their interaction, at runtime. SHSA has to be enabled and supported by the underlying platform, in order to minimize undesired interference during components exchange and to reduce the complexity of the application components. In this paper, we discuss architectural requirements and design decisions which enable SHSA in CPS. We propose a platform that facilitates structural adaptation and demonstrate its capabilities on an example from the automotive domain: a fault-tolerant system that estimates the state-of-charge (SoC) of the battery. The SHSA support of the SoC estimator is enhanced through the existence of an ontology, capturing the interrelations among the components and using this information at runtime for reconfiguration. Finally, we demonstrate the efficiency of our SHSA framework by deploying it in a real-world CPS prototype of a rover under sensor failure. Denise Ratasich, Oliver Höftberger, Haris Isakovic, Muhammad Shafique 0001, Radu Grosu |
ISORC | 3 |
| 2016 | The EMC2 Project on Embedded Microcontrollers: Technical Progress after Two YearsabstractSince April 2014 the Artemis/ECSEL project EMC2 is running and provides significant results. EMC2 stands for "Embedded Multi-Core Systems for Mixed Criticality Applications in Dynamic and Changeable Real-Time Environments". In this paper we report recent progress on technical work in the different workpackages and use cases. We highlight progress in the research on system architecture, design methodology, platform and operating systems, and in qualification and certification. Application cases in the fields of automotive, avionics, health care, and industry are presented exploiting the technical results achieved. Werner Weber, Alfred Hoess, Jan van Deventer, Frank Oppenheimer, Rolf Ernst, Adam Kostrzewa, Philippe Dore, Thierry Goubier, Haris Isakovic, Norbert Druml, Egon Wuchner, Daniel Schneider 0001, Erwin Schoitsch, Eric Armengaud, Thomas Soderqvist, Massimo Traversone, Sascha Uhrig, Juan-Carlos Perez-Cortes, Sergio Sáez, Juha Kuusela, Mark van Helvoort, Xing Cai, Bjørn Nordmoen, Geir Yngve Paulsen, Hans Petter Dahle, Michael Geissel, Jürgen Salecker, Peter Tummeltshammer |
DSD | 9 |
| 2014 | Virtual CAN Lines in an Integrated MPSoC ArchitectureabstractThe standard solution for automotive control networks is the Control Area Network (CAN) bus. Almost any vehicular computer system comprehends at least one CAN line. For the past two decades, software development for control system has been strongly connected to the properties and interfaces of the CAN bus. Currently, the automotive industry is in the middle of a technology leap towards an information-based industry. New technologies are getting ready to fulfill newly emerging requirements for innovative products such as hybrid engine control, intelligent energy management, and advanced driver assistance systems. Integrated Multi-Processor-on-a-Chips (MPSoCs) will be one part of the solution to provide an adequate computing infrastructure for these newly emerging systems. The established technologies like the CAN bus will have to be reconsidered. In this work, we propose a virtual CAN overlay that abstracts the communication interfaces of an MPSoC to provide the Application Programmer Interface (API) of CAN to programmers. The overlay provides the standard behavior of a CAN line and works transparently over chip boundaries. The major implications is that the programmers can continue their used software development approaches and tools when introducing a new computing infrastructure. The main benefit is that the productivity can be maintained during this critical phase. In summary, our solution helps to mitigate the effects from a technology shift to integrated MPSoCs. Our approach is fully compliant with new automotive software development approaches like AUTOSAR. Armin Wasicek, Oliver Höftberger, Martin Elshuber, Haris Isakovic, Andreas Fleck |
ISORC | 4 |
| 2013 | Secure channels in an integrated MPSoC architectureabstractProviding security in an embedded system often boils down to solving a trade-off problem between security and performance. Simultaneously, Multi-Processor System-on-a-Chip (MPSoC) devices are in the early stages to increase computational performance, energy and die area efficiency, and reduce the number of physical units in the embedded system design arena. Moreover, MPSoCs enable composing heterogeneous subsystems on a single silicon die which is particularly desirable for large volume embedded devices. However, these benefits come at a price: an increase in the system's complexity. Complexity does not only make the system design process more difficult, but also it renders certain vulnerabilities possible. A solution is to follow well-established architectural principles to reduce complexity and to provide the required level of security. In this paper we demonstrate how the basic architectural principles of the ACROSS MPSoC architecture can be combined with the requirements of standard security techniques (i.e., encryption, authentication) to produce an efficient security solution for MPSoC systems. We propose a security architecture which uses the principles of temporal and spatial partitioning, temporal determinism, and mixed-criticality integration to migrate resource expensive security functions form the application components to a dedicated security component within the MPSoC. This leaves application components with a thin security provider, without any loss of functionality and more local resources at their disposal. Thereby, we deliver a flexible, resource efficient security solution, which highlights the benefits of partitioning MPSoC architectures for security. Haris Isakovic, Armin Wasicek |
IECON | 1 |
| 2012 | The ACROSS MPSoC - A New Generation of Multi-core Processors Designed for Safety-Critical Embedded SystemsabstractThe European ARTEMIS ACROSS project aims to overcome the limitations of existing Multi-Processor System-on-a-Chip (MPSoC) architectures with respect to safety-critical applications. MPSoCs have a tremendous potential in the domain of embedded systems considering their enormous computational capacity and energy efficiency. However, the currently existing MPSoC architectures have significant limitations with respect to safety-critical applications. These limitations include difficulties in the certification process due to the high complexity of MPSoCs, the lacking temporal determinism and problems related to error propagation between subsystems. These limitations become even more severe, when subsystems of different criticality levels have to be integrated on the same computational platform. Examples of such mixed-criticality integration are found in the avionics and automotive industry with their desire to integrate safety-critical, mission critical and non-critical subsystems on the same platform in order to minimize size, weight, power and cost. The main objective of ACROSS is to develop a new generation of multicore processors designed specially for safety-critical embedded systems; the ACROSS MPSoC. In this paper we will show how the ACROSS MPSoC overcomes the limitations of existing MPSoC architectures in order to make the multi-core technology available to the safety-critical domain. Christian El Salloum, Martin Elshuber, Oliver Höftberger, Haris Isakovic, Armin Wasicek |
DSD | 4 |