Network on chip (NoC) is an infrastructure providing a communication platform to multiprocessor chips. Furthermore, the wormhole-switching method, which shares resources, was used to increase its efficiency; however, this can lead to congestion. Moreover, dealing with this congestion consumes more energy and correspondingly leads to increase in power consumption. Furthermore, consuming more power results in more heat and increases thermal fluctuations that lessen the life span of the infrastructures and, more importantly, the network’s performance. Given these complications, providing a method that controls congestion is a significant design challenge. In this paper, a fuzzy logic congestion control routing algorithm is presented to enhance the NoC’s performance when facing congestion. To avoid congestion, the proposed algorithm employs the occupied input buffer and the total occupied buffers of the neighboring nodes along with the maximum possible path diversity with minimal path length from instant neighbors to the destination as the selection parameters. To enhance the path selection function, the uncertainty of the fuzzy logic algorithm is used. As a result, the average delay, power consumption, and maximum delay are reduced by 14.88%, 7.98%, and 19.39%, respectively. Additionally, the proposed method enhances the throughput and the total number of packets received by 14.9% and 11.59%, respectively. To show the significance, the proposed algorithm is examined using transpose traffic patterns, and the average delay is improved by 15.3%. The average delay is reduced by 3.8% in TMPEG-4 (treble MPEG-4), 36.6% in QPIP (quadruplicate PIP), and 20.9% in TVOPD (treble VOPD).

As the number of on-chip processor cores increases, power-efficient solutions are sought for data communication between cores. TheHelix-hnon-blocking photonic switch is developed to improve physical-layer and network performance parameters for a wide range of silicon nano-photonic multicore interconnection topologies. Traffic benchmarks and practical case studies using a cycle-accurate simulation environment indicate significantly reduced insertion loss providing improved bandwidth density and scalability to manycore plurality. Improvements in system performance parameters are quantified for network bandwidth, transmission efficiency, and latency in popular photonic internconnection topologies, in comparison to previous switch designs. For instance, utilizing the Helix-h switch in a mesh topology, the bandwidth is increased by 112 percent compared to the previously highest performing switch design. Execution time and energy efficiency are improved by up to 92 and 99 percent, respectively, for representative multicore applications. Finally, the technique is generalized to a novel graph-theoretic method for articulating blocking conditions in photonic switches.

Researches demonstrate that overheating can raise the risk of failure in electrical chips. Also, increasing processing demand of applications increase the number of IPCores inside the chips and subsequently make them being tightly coupled, which in turn can intensify the thermal issues. In this paper we propose an application specific temperature-aware mapping algorithm which maps IPCores such that thermal correlation between them would be taken as minimum with considering the performance impact. Simulation results show that the average peak temperature is reduced while applying our mapping onto four application graphs. Moreover the communication cost and energy consumption are also reduced.