Multicore embedded systems have evolved to appear in different domains. In this paper, we explore and compare various on-chip architectures with respect to a number design metrics. Unlike earlier published works that majorly concern with optimizations in processor, memory and cache hierarchies, in this paper, we aim to ascertain the best on-chip architectures for given processor cores, Level 1-2-3 caches modeled from Intel Atom embedded processor family. We investigate topologies that haven't been considered before for symmetric multiprocessing in embedded systems domain. These architectures consist of shared instruction caches between cores and heterogenous cache topologies that feature bypassing a level in the cache hierarchy. Through our experiments with multithreaded workloads, we elicit the unconventional topologies that could provide more performance and energy efficiency than regular topologies. In addition, using our experimental data, we conclude that certain design metrics could depend on given workload, however there also exists some metrics that are more dependent on the the underlying topologies. Thus, we urge the need for future exploration tools to gather the necessary metrics while choosing the appropriate SMP architectures.

Recently, with the rise of Internet of Things and Big Data, acceleration of database analytics in order to have faster query processing capabilities has gained significant attention. At the same time, High-Level Synthesis (HLS) technology has matured and is now a promising approach to design such hardware accelerators. In this work, we use a modern HLS, Vivado to design high-performance database accelerators for filtering, aggregation, sorting, merging and join operations. Later, we use these as building blocks to implement an acceleration system for in-memory databases on a Virtex-7 FPGA, detailed enough to run full TPC-H benchmarks completely in hardware. Presenting performance, area and memory requirements, we show up to 140x speedup compared to a software DBMS, and demonstrate that HLS technology is indeed a very appropriate match for database acceleration.

FPGA block RAMs (BRAMs) offer speed advantages compared to LUT-based memory designs but a BRAM has only one read and one write port. Designers need to use multiple BRAMs in order to create multi-port memory structures which are more difficult than designing with LUT-based multiport memories. Multi-port memory designs increase overall performance but comes with area cost. In this paper, we present a fully automated methodology that tailors our multi-port memory from a given application. We present our performance improvements and area tradeoffs on state-of-the-art string matching algorithms.

This work presents a synthesis framework that generates a formally verifiable RTL from a high level language. We develop an estimation model for area, delay and power metrics of arithmetic components for Xilinx Spartan 3 FPGA family. Our estimation model works 300 times faster than Xilinx's toolchain with an average error of 6.57\% for delay and 3.76\% for area estimations. Our framework extracts CDFGs from ANSI-C, LRH(+) [1] and VHDL. CDFGs are verified using the symbolic model checker NuSMV [2] with temporal logic properties. This method guarantees detection of hardware redundancy and word-length mismatch related bugs by static code checking.