The optical test of CMOS Image Sensors (CIS) represents a major part of the overall test time. It consists in applying two-dimensional image processing algorithms on the output images of the CIS under test. In [1], we demonstrated that it is possible to embed 50% of these algorithms in the CIS by using a dedicated Built-In Self-Test (BIST) engine without impacting the defect coverage and at a negligible area cost (approximately 0.25% of the total sensor area). The use of a BIST solution reduces the optical test time by roughly 30% when compared to the optical algorithms traditionally applied by using an Automatic Test Equipment (ATE). However, the effectiveness of this approach is limited by the fact that some global subtle defects cannot be detected. This is a real problem as these defects can seriously impact the output image quality. To overcome this drawback, this paper presents a new BIST solution, called Predictor BIST (PRED BIST) based on a global overview of the image under test. The novelty of this approach lies in the use of an arithmetic method to build an ideal (i.e., predicted) image from wisely selected samples extracted from each output image of the CIS under test. The process of building an ideal image is repeated for all images to be checked for the CIS under test. By comparing each output image to the ideal image, it is then possible to classify good and bad images. Moreover, PRED BIST is an all-in-one test solution that allows to fully replace the optical test done today with an ATE by an embedded test solution. This is an important and unique feature of PRED BIST. Two databases were used to validate this new BIST solution. The first one is an extension of the monocolor database of 27,600 images used in [2] and the second one contains 81,840 images from a RGB sensor. Validation shows that compared to conventional ATE-based test, a correlation of 99.90% and 99.40% respectively is achieved regarding the classification between good and bad images of two considered databases. Moreover, the global defects missed by the test solution in [1] are always found by PRED BIST. This new test solution results in a reduction of up to 95% of the optical test time.

This paper demonstrates the generalization of a novel test solution embedded inside CMOS Image Sensors (CIS) to classify PASS/FAIL sensors during the test production phase. In [1], a Built-In Self-Test (BIST) solution was proposed to reduce the test time of a CIS, which can represent up to 30% of the final product cost. The major part of the test is dedicated to optical (i.e. image processsing) algorithms performed on the output images from the sensor under test with an Automatic Test Equipment (ATE). The BIST solution reuses these optical algorithms by simplifying and embedding them inside the sensor, to avoid a large amount of data storage and to limit the optical test time. First results on 4,800 output images from a package of sensors have shown a 99.95% correlation between results gathered from an ATE and those achieved with the proposed BIST, with a saving of approximately 30% in optical test time and a negligible area footprint. In this paper, to verify the effectiveness of the BIST solution on a wider set of different CIS (i.e., architecture, size and technology), we experimented the solution on a new database of 28,000 output images from a package of different sensors compared to the first package used in [1]. The BIST parameters have been configured to fit with the new type of sensors and results show a 99.64% correlation, which demonstrates the possible systematic implementation of the proposed BIST solution inside all CIS irrespective of their architecture and technology.

This paper presents a novel test solution directly embedded inside CMOS Image Sensors (CIS) to sort out PASS and FAIL dies during production test. The solution aims at reducing test time, which can represent up to 30% of the final product cost. By simplifying the way optical tests are usually applied with an ATE, the proposed Built-In Self-Test (BIST) solution overcomes the drawbacks of long test time and huge amount of test data storage. We experimented our solution by considering that roughly half of the tests usually performed with an ATE can be embedded and applied using the proposed fast and low cost BIST engine. Results obtained on more than 2,400 sensors have shown that our solution reduces test time by about 30% without impacting the defect coverage. The area cost of our solution is about 1% of the digital part of the sensor, i.e., approximately 0.25% of the total sensor area. The proposed embedded CIS test solution outperforms existing solutions in terms of area overhead and test time saving, thus encouraging its future implementation in an industrial production flow.

With the continued down-scaling of IC technology and increase in manufacturing process variations, it is becoming ever more difficult to accurately estimate circuit performance of manufactured devices. This poses significant challenges on the effective application of adaptive voltage scaling (AVS) which is widely used as the most important power optimization method in modern devices. Process variations specifically limit the capabilities of Process Monitoring Boxes (PMBs), which represent the current industrial state-of-the-art AVS approach. To overcome this limitation, in this paper we propose an alternative solution using delay testing, which is able to eliminate the need for PMBs, while improving the accuracy of voltage estimation. The paper shows, using simulation of ISCAS’99 benchmarks with 28nm FD-SOI library, that using delay test patterns result in an error of 5.33% for transition fault testing (TF), error of 3.96% for small delay defect testing (SDD), and an error as low as 1.85% using path delay testing (PDLY). In addition, the paper also shows the impact of technology scaling on the accuracy of delay testing for performance estimation during production. The results show that the 65nm technology node exhibits the same trends identified for the 28nm technology node, namely that PDLY is the most accurate, while, TF is the least accurate performance estimator.

Adaptive voltage scaling (AVS) has been used widely to compensate for process, voltage, and temperature variations as well as power optimization of integrated circuits. The current industrial state-of-the-art AVS approaches using Process Monitoring Boxes (PMBs) have shown several limitations such as huge characterization effort, which makes these approaches very expensive, and a low accuracy that results in extra margins, which consequently lead to yield loss and performance limitations. To overcome those limitations, in this paper we propose an alternative solution using transition fault test patterns, which is able to eliminate the need for PMBs, while improving the accuracy of voltage estimation. The paper shows, using simulation of ISCAS'99 benchmarks with 28nm FD-SOI library, that AVS using transition fault testing (TF-based AVS) results in an error as low as 5.33%. The paper also shows that the PMB approach can only account for 85% of the uncertainty in voltage measurements, which results in power waste, while the TF-based approach can account for 99% of that uncertainty.

In deep sub-micron technologies, the increasing effect of process and environmental variations has lead chip manufacturers to use adaptive voltage scaling techniques in order to adapt operation parameters exclusively to each chip. The increasing effect of process variation is limiting the effectiveness of current chip monitoring approaches, such as on-chip performance monitor boxes (PMBs), which results in yield loss and high design margins, thus high power consumption. This paper proposes an alternative solution for adaptive voltage scaling using delay test patterns, which is able to eliminate the need for PMBs, and thus the long expensive characterization phase of tuning PMBs to each design, while improving the yield as well as power optimization. Results show, using an industrial grade 28nm FD-SOI library developed for low power devices, that delay testing for performance prediction reduces the inaccuracy down to 1.85%.

Power-gating techniques have been adopted so far to reduce the static power consumption of an Integrated Circuit (IC). Power-gating is usually implemented by means of several power switches. Manufacturing defects affecting power switches can lead to increase the actual static power consumption and, in the worst case, they can completely isolate a functional block in the IC. Thus, efficient test and diagnosis solutions are needed. In this paper we propose a Design-for-Diagnosis architecture for Power Switches. The proposed approach has been validated through SPICE simulations on ITC'99 benchmark circuits as well as on industrial test case.

Power-gating techniques have been adopted so far to reduce the static power consumption of an Integrated Circuit (IC). Power gating is usually implemented by means of several power switches. Manufacturing defects affecting power switches can lead to increase the actual static power consumption and, in the worst case they can completely isolate a functional block of the IC. In this paper we present a novel Design for Test & Diagnosis to increase the test quality and diagnosis accuracy of power switches. The proposed approach has been validated through SPICE simulations on ITC'99 benchmark circuits.

In this paper we propose a novel Power Supply Noise (PSN) sensor. It is based on timing uncertainty measure. Compared to state of the art it allows to measure the PSN events in more accurate way. The proposed sensor is actually under validation and patent reviewing process.

In this work, we present a new power supply noise sensor based on timing uncertainty measurements. The proposed sensor can detect power supply noise events in a more accurate way compared to the state of the art solutions. Experimental results validated the efficiency of the proposed approach.