This paper presents a self-compensating StrongARM latch topology tailored for high-speed and energy-efficient true random number generator (TRNG) design. Unlike conventional approaches that rely on auxiliary controllers to monitor the output and apply compensation, the proposed latch incorporates a coupling capacitor and internal feedback path, which autonomously mitigate offset voltages induced by transistor mismatch. This inherent self-compensation not only simplifies the overall architecture but also improves robustness against PVT variations. A TRNG prototype is realized by integrating four self-compensating StrongARM latches with a lightweight XOR-based post-processing stage, thereby ensuring high-quality randomness with minimal design complexity. The statistical properties of the generated bitstreams are verified through NIST SP 800-22 and NIST SP 800-90B test suites, confirming compliance with standard randomness and robustness requirements. Post-layout simulations in a 65-nm low-power CMOS process demonstrate that the proposed TRNG achieves a throughput of 2 Gbps while consuming only 0.107 pJ/bit, highlighting its suitability for energy-constrained security applications.

This paper proposes a switched-capacitor DC-DC converter with a self-recovery hysteresis control mechanism to deal with both steplike and spike-like load fluctuations. The converter is fabricated in a commercial 65 nm CMOS low-power (LP) process. Our converter can maintain efficiency above 69% over a load current range of 0.11~ 8.0mA with a total capacitance of 1 nF. The converter recovers quickly from a current spike of as high as 21mA within only 92 mV of voltage drop.

This paper presents measurement results of a flash ADC that utilizes offset voltages as references. To operate the minimum number of comparators, we select the target comparators based on the rankings of the offset voltage. We present performance improvement by tuning offset voltage distribution using multiple comparator groups under the same power. A test chip in a commercial 65 nm GP process demonstrates the ADCs at 1 GS/s operation.

This paper proposes a synchronous digital LDO with adaptive clocking and dead-zone control without additional reference voltages. A test chip fabricated in a commercial 65 nm CMOS general-purpose (GP) process achieves 580x frequency modulation with 99.9% maximum efficiency at 0.6V supply.

This paper proposes a parameter extraction method by comparing the cumulative distribution functions (CDF) between measurement and model-based estimation. We propose a nonlinear delay variation model for fast Monte Carlo simulation to obtain CDFs. We demonstrate the validity of our method by extracting within-die and random telegraph noise induced threshold voltage variations using measured data obtained from a 65 nm test structure. Our proposed method can accurately extract the statistical parameters and can reproduce the measured delay variations by simulation.

In addition to the conventional PVT (Process, Voltage and Temperature) variation, time-dependent current fluctuation such as random telegraph noise (RTN) poses a new challenge on VLSI reliability. In this paper, we show that compared with the static random variation, RTN amplitude of a particular device is not constant across supply voltages and temperatures. A device may show large RTN amplitude at one operating condition and small amplitude at another operating condition. As a result, RTN amplitude distribution becomes uncorrelated across a wide range of voltage and temperature. The emergence of uncorrelated distribution causes significant degradation of worst-case values. Analysis results based on variability models from a 65 nm silicon-on-insulator process show that uncorrelated RTN degrades the worst-case threshold voltage value significantly compared with that where RTN is not considered. Delay variation analysis shows that consideration of RTN in the statistical analysis have little impact at high supply voltage. However, at low voltage operation, RTN can degrade the worst-case value by more than 5%.

Aggressive technology scaling and strong demand for lowering supply voltage impose a serious challenge in achieving robust and energy-efficient circuit operation. This paper first overviews on device-circuit interactions to enable cross-layer resiliency, and energy optimization. We show that the ability to monitor and control device and circuit characteristics not only increase energy-efficiency by more than 20% but also relax the severe design constraints, which were required because of the uncertainties of variability. We then demonstrate two proof-of-concept circuits in a 65 nm process to show variability resiliency and energy optimization with local body biasing.

This paper proposes the use of ROs (Ring Oscillators) for process shift and process spread detection for silicon debugging and model-hardware correlation. ROs are designed to be sensitive to either nMOSFET orpMOSFET variation, thus the location of the chip in the process spacecan be detected directly from the RO measurements. Test chip measurements in a 65-nm process shows the validity of the proposed ROs. Amounts of process shift and process spread for key process parameters as threshold voltages and gate length are extracted from test chip measurements.