The exponential complexity of automatic test pattern generation (ATPG) necessitates the use of heuristics in making choices during test generation. However, in practice no single heuristic fits all situations. Unsupervised learning can combine any number of known heuristics, such as input-output distance (logic depths), gate type, fanout information, and testability measures like Controllability and Observability Program (COP) and Sandia Controllability/Observability Analysis Program (SCOAP) through principal component (PC) analysis, and then the major PC can guide ATPG choices. This study combines three heuristics, distance, COP, and SCOAP. Some heuristic data are complemented and two major PC are obtained. These PC guide backtrace directions in a PODEM ATPG program. For most circuits, the number of backtracks either matches the best of the three heuristics or is lower than all.

Technology scaling cannot meet consumer demands, especially for binary circuits. Previous studies proposed addressing this with multi-valued logic (MVL) architectures, but these architectures use non-standard fabrication techniques and optimistic performance analysis. This study presents a new quaternary FPGA (QFPGA) architecture based on floating-gate memories that standard CMOS fabrication can fabricate: programming floating-gates implement a voltage divider, and these divided voltages represent one of four distinct logic values. When simulated with open-source FinFET SPICE models, the proposed architecture obtains competitive delay and power performance compared to equivalent binary and QFPGA architectures from literature. Results show the proposed QFPGA basic logic element (BLE) requires half the area and dissipates a third of the power density compared to QFPGA architectures from literature. When projecting BLE performance onto benchmark circuits, implementing circuits requires up to 55% less area and one-third the power, and the proposed architecture can operate at clock speeds up to three times faster than binary equivalents. Future studies will investigate accurate modeling of interconnects to better account for their performance impacts and will explore efficient architectures for programming MVL memories when they're used in FPGAs.

Integrated circuit (IC) testing presents complex problems that, when ICs become large, are exceptionally difficult to solve by traditional computing techniques. To deal with unmanageable time complexity, engineers often rely on human “hunches” and “heuristics” learned through experience. Training machines to adopt these human skills is called machine learning (ML). This survey examines applications of ML to testing analog, digital, memory, radio frequency (RF), and other application based ICs. This survey then highlights significant challenges and potential research directions.

A new quaternary FPGA (QFPGA) architecture based on floating-gate memories is presented and analyzed. Technology scaling has delivered substantial FPGA performance, but consumer demands grow beyond binary circuit capabilities. Non-binary FPGAs have been explored, but previous architectures use non-standard fabrication and optimistic performance analysis. The proposed QFPGA based on floating-gate memories has competitive power performance compared to contemporaries QFPGA architectures from literature when simulated FinFET technology.

This study examines machine intelligence's (MI) ability to enhance automatic test pattern generation (ATPG) by reducing backtracks. In lieu of a conventional heuristic to decide backtracing directions, this study uses an artificial neural network (ANN) trained through PODEM on hard-to-detect faults. Training data contains topological data, testability measures, and backtracking history, and when trained on this data, the ANN guides backtracing in directions unlikely to backtrack. When trained with a single feature (e.g., COP), ATPG performance is comparable to conventional PODEM, and using multiple features further reduces backtracks and ATPG CPU time.

This article surveys test point (TP) architectures and test point insertion (TPI) methods for increasing pseudo-random and logic built-in self-test (LBIST) fault coverage. We present a history of TPI approaches, including TPI for increasing stuck-at fault coverage, compressing test patterns, detecting path delay faults, and reducing test power. We discuss some known weaknesses of TPs and explore research directions to overcome them.

This article presents methods of increasing logic built-in self-test (LBIST) delay fault coverage using artificial neural networks (ANNs) to selecting test point (TP) locations a method to train ANNs using randomly generated circuits. This method increases delay test quality both during and after manufacturing. This article also trains ANNs without relying on valuable third-party intellectual property (IP) circuits. Results show higher-quality TPs are selected in significantly reduced CPU time and third-party IP is not be required for ANN training.

This article presents a brief survey of digital delay fault testing, which lists 100+ references on fault models, simulators, ATPG, DFT, and tools. Continuing studies are needed in this maturing field for new technologies, signal integrity, process variations, faster than critical path operation, asynchronous circuits, counterfeit ICs, and hardware Trojans. This information is compiled to provide direction to students, practicing engineers, and researchers alike.

Various techniques for modern high performance designs, such as clock gating and dynamic voltage frequency scaling (DVFS), have been adapted to address power issues. This is a consequence of technology scaling and it is important and desirable to address reliability needs as well as economic issues. From a testing point of view, introduction of power constraints during testing is needed for the desired product quality and to avoid yield loss. Unlike designers who have often benefited from the design for test hardware introduced for testing, test engineers have rarely taken advantage of the extra hardware introduced to meet design needs. In this paper, we make use of the DVFS technology and its associated hardware to improve test economics. We formulate the power constrained testing problem as an optimization problem that makes use of DVFS technology. We show that we can obtain superior test schedules for both session-based and session less testing methods relative to existing and traditional methods of obtaining test schedules.

With technology scaling towards smaller geometries, the power density of modern integrated circuits (ICs) can potentially result into high temperatures during test, a problem further compounded by stacking dies in 3D stacked structures (3DSICs). Scheduling tests in a way to minimize the total test time becomes a key issue when temperature constraints are involved, since a more compact schedule leads to a hotter device. Unfortunately, many previous attempts at temperature-bounded scheduling either use inferior temperature models leading to under compaction, or they can only be applied to traditional single-die designs. Simple thermal models based on steady state temperatures are inadequate to schedule tests in 3DSICs due to their limitations. This paper proposes two formulations for test scheduling under thermal constraints for 3DSICs using the superposition principle, which allows for accurate thermal modeling and superior test compaction. This paper then compares them to previous formulations which use steady-state models, and also discusses the inherent limitations of the steady-state model. Results of the algorithms proposed in this paper show the superiority of the schedules obtained for testing 3DSICs.