Integrating subsystems developed by different manufacturers is a challenging task. Nevertheless, in fields like Intelligent Transport Systems (ITS), it is imperative for vehicles and infrastructure to constantly communicate. The proposed method models elements from a Threat Analysis and Risk Assessment (TARA) of each subsystem using SysML. Then it applies compatibility conditions to the exported model to generate an output compatibility statement. This statement indicates whether the subsystems are compatible from a security perspective or not. The method enables subsystems to assess their potential for secure integration allowing for independent development by manufacturers. We implement the method and evaluate it on an industrial use case to showcase the method's ability to determine the security compatibility of two subsystems.

Error injection has become critically important for testing the reliability of newly designed hardware systems. Evaluating how a design under test (DUT) reacts to different error-injection methodologies is essential for verification engineers to design dependable universal verification methodology (UVM) scoreboards for error-detection purposes. The first main contribution of this paper is to decide on the feasibility and compatibility of some error-injection techniques when used with networks-on-chip (NoC) platforms for simulation and hardware emulation environments. We target a UVM-based error-injection and detection environment with reusable components. Proposed techniques, introducing both positive and negative test scenarios, are applied to two examples of NoC components: 1) a base router and 2) Daniel router. Base router is a simple case study to prove proposed schemes, whereas Daniel router is a complex reconfigurable open-source case study. Daniel router provides the ability to change router architecture with some parameters and applied algorithms. The second main contribution of this paper is to integrate a full UVM environment with various verification approaches. Target approaches include error injection and detection using reusable and generic UVM environment and components for NoC. Network response is inspected according to error type and methodology. Finally, the proposed UVM environment is used to test and verify an N × N 2-D network composed of base routers or Daniel routers.

Integrated framework to simulate electronic system (including digital and analog devices) with the mechanical parts of a heterogeneous automotive system is presented. The electronic system, consisting of many Electronic Control Units (ECUs), is modeled to simulate the mechatronic system functionality. The recently developed Functional Mock-up standard approach is used to have a model for a complex cyber-physical automotive system. The framework simulates real system including the Hardware (HW) and the Software (SW) to run on the ECUs. It allows Co-development of the automotive system SW and HW while the mechanical system is in the loop. Hardware and Software debugging is demonstrated using the developed methodology. The development cycle for the automotive mechatronic system could be greatly shortened using the proposed framework.

With the increase in the number of cores embedded on a chip; The main challenge for Multiprocessor System-on-Chip (MPSoC) platforms is the interconnection between that massive number of cores. Networks-on-Chip (NoC) was introduced to solve that challenge, by providing a scalable and modular solution for communication between the cores. In this paper, we introduce a configurable MPSoC framework called RVNoC that generates synthesizable RTL that can be used in both ASIC and FPGA implementations. The proposed framework is based on the open source RISC-V Instruction Set Architecture (ISA) and an open source configurable flit-based router for interconnection between cores, with a core network interface of our design to connect each core with its designated router. A benchmarking environment is developed to evaluate variant parameters of the generated MPSoC. Synthesis of a single building block containing a single core without any peripherals, a router, and a core network interface, using 45nm technology, shows an area of 102.34 kilo Gate Equivalents (kGE), a maximum frequency of 250 MHz, and a 9.9 μW/MHz power consumption.

A multi-processor system is an integrated circuit containing multiple processor cores that implements most of the functionality of a complex electronic system and some other components like FPGA/ASIC on a single chip. In this paper, we present a novel approach to synthesize multi-core system architectures from Task Precedence Graphs (TPG) models. The front end engine applies efficient algorithm for scheduling and communication contention resolving to obtain the optimal multi-core system architecture in terms of number of processor cores, number of busses, task-to-processor/channel-to-bus mapping, optimal schedule, and hardware-software (HW-SW) partition. The scheduling and mapping algorithms produce the optimality of mapping tasks onto cores. The partitioning technique reduces the overall execution time and number of buses among the cores. The back end engine generates a SystemC simulation model using a well-known commercial tool model generation library. The viability and potential of the proposed algorithms are demonstrated by a case study and extensive experimental results to conclude that the proposed approach is an efficient scheme to obtain the optimality of scheduling, mapping and partitioning with hard and large task graph problems.

Two oscillator circuits designed in 45 nm technology incorporating an integrated capacitive vibrating Micro Electro Mechanical (MEMS) resonator for microprocessor applications are presented. The general topology of the oscillator is based on a shunt-shunt feedback transimpedance amplifier with an automatic gain control circuit to ensure linear operation of the integrated resonator to reduce the oscillator 1/f3phase noise component introduced by the resonator nonlinear capacitive transducer. Two different topologies for the transimpedance amplifier are presented: the first topology uses a self biased fully differential amplifier while the second topology uses a multi stage gm-boosting amplifier with a negative feedback amplifier for self biasing. The designed circuits operate robustly across all process corners and across 120°C temperature range from -10°C to 110°C while consuming less than 8 mW power and occupying an area of 300um×255um and phase noise of -120dBC/Hz at 200KHz offset. The designed circuits are the first implementation of a MEMS based oscillator in deep submicron processes showing robust performance across all process corners and variations.