One approach for achieving a robust integrated system centers on first performing test during runtime, then identifying the locations of any faults (or potential faults), and finally repairing/replacing/avoiding the affected portion(s) of the system. Conventional fault dictionary approaches can be used to locate failures but are limited to simplistic fail behaviors due to the significant computational resources required for dictionary generation and memory storage. Several contributions are described to overcome these limitations, and include: 1) enhancement of an unspecified-transition fault model (called here the transition-X fault model, or TRAX) for capturing the misbehaviors expected from scaled technologies; 2) development of a hierarchical dictionary that only localizes to the level required; and 3) the design of a scalable architecture for retrieving and using the hierarchical dictionary for on-chip failure diagnosis. The OpenSPARC T2 processor and other circuits are used in experiments to demonstrate the low-overhead, accurate diagnosis of early life and wear-out failures, using TRAX dictionaries that are over five orders of magnitude smaller than full-response dictionaries.

This paper presents the design and implementation of a fault simulator for the TRAnsition-X fault model (TRAX for short) on a graphics processing unit (GPU). Fault dictionaries are an important aspect of on-chip fault detection and diagnosis. Generating a fault dictionary requires fault simulation with no fault dropping, requiring extensive computational resources. The inherent parallelism of the fault simulation problem maps well to the large number of concurrent threads supported by a modern GPU, and a GPU can be used to accelerate the construction of a fault dictionary. Our approach employs both pattern-parallel and fault-parallel algorithms in the GPU kernel implementations. Experiments involving various circuits, including the OpenSPARC T2 processor, demonstrate a speed-up of over 42x.

To ensure robustness of integrated systems, the TRAnsition-X (TRAX) fault model has been used with on-chip test and diagnosis hardware, utilizing fault dictionaries for diagnosis. Generating a fault dictionary requires fault simulation with no fault dropping, requiring extensive computational resources. This paper presents the design and implementation of an efficient fault simulator for the TRAX fault model, designed to run on a graphics processing unit (GPU). The inherent parallelism of the fault simulation problem maps well to the large number of concurrent threads supported by a modern GPU, and a GPU can be used to accelerate the construction of a fault dictionary. Our approach employs both pattern-parallel and fault-parallel algorithms in the GPU kernel implementations. Experiments involving various circuits, including the OpenSPARC T2 processor, demonstrate a mean speed-up of nearly 8x.

One approach for achieving integrated-system robustness centers on performing test during runtime, identifying the location of any faults (or potential faults), and repairing or avoiding the affected portion of the system. Fault dictionaries can be used to locate faults but conventional approaches require significant memory storage and are therefore limited to simplistic fault types. To overcome these limitations, three contributions are made that include: (i) enhancement of an unspecified transition fault model (called here the transition-X fault model, or TRAX for short) for capturing the misbehaviors expected from scaled technologies, (ii) development of a new type of hierarchical dictionary that only localizes to the level of repair or fault avoidance, and (iii) the design of a scalable architecture for retrieving and using the hierarchical dictionary for performing on-chip diagnosis. Experiments involving various circuits, including the OpenSPARC T2 processor, demonstrate that early-life and wear-out failures can be accurately diagnosed with minimum overhead using TRAX dictionaries that are up to 2600x smaller than full-response dictionaries.