The exponential growth in test data volume for modern Systems-on-Chip (SoCs), combined with a decreasing number of available test pins, has led to increased test time and complexity. Simultaneously, the industry’s drive for higher quality and lower Defective Parts Per Million (DPPM) necessitates continuous monitoring, testing, and repair Silicon Lifecycle Management (SLM). The advent of multi-die packaging technologies, such as 2.5D and 3D stacked integration, further exacerbates these challenges by introducing additional layers of interconnect and access constraints.Universal Chiplet Interconnect Express (UCIe) emerges as a compelling solution for delivering test content to all constituent dies at-speed, post-packaging. UCIe enables seamless test access across various lifecycle stages, including wafer sort, package test, System Level Test (SLT), and In-System Test (IST).This paper introduces a silicon-proven methodology that integrates the UCIe protocol with advanced SLM techniques to address the critical challenges of access, test, measurement and repair in complex multi-die SoC designs. Silicon results from test vehicles fabricated on TSMC N3P process with CoWoS-S packaging demonstrate complete interconnect, logic, and memory test, repair, and monitoring capabilities, validating the effectiveness and scalability of the proposed approach for next- - generation multi-die systems.

Integrated passive devices (IPDs) have been widely used in advanced packaging of semiconductor chips, to improve their power integrity and impedance matching. There is a growing demand in guaranteeing signal and power integrity for the chips used in safety-critical products, such as those used in automotive, aviation, industrial, and defense systems, where IPDs help improve quality and reliability of the chips. Therefore, IPD testing and screening itself is essential. Note that the cost of replacing failed IPDs is much higher than the cost of manufacturing them, so screening bad IPDs before mounting is also crucial. In this work, we propose a machine learning (ML) based screening methodology to identifying the IPDs that have potential reliability issues. Based on the parametric data of 360,000 IPDs collected from the wafer probing test, the proposed Semiconductor Quality Net (SQnet) is trained to predict the IPDs which have low breakdown voltage, i.e., low reliability. Keeping the overkill rate below 10%, our method can screen out 6 to 15X more bad dies than the existing industrial methods, i.e., DPAT and GDBC.

This paper introduces an anomaly detection methodology with machine learning for Circuit Probing (CP) using Integrated Passive Device (IPD) as example devices. The IPD can improve the power integrity, performance, and package dimensions of the Integrated Fan-Out Package on Package (InFO-PoP), which is more cost-effective than 3D Integrated Circuits (3DIC) to achieve “More than Moore's law” for mobile devices. Because a defective IPD can invalidate the entire package, the previous test methods are dedicated to very high-end screening for the underkill/failure-escape of high quality and reliable devices. On the other hand, the overkill issues are not concerned yet, which periodically impact the yield and cost. In this paper, we propose a new flow with machine learning methodologies to detect previously ignored anomalies on site-aware wafer-maps for predictive maintenance. The proposed flow covers the overkill and re-test issues to complete the high-quality and cost-effective test methodology with test defense.

This paper introduces a novel test methodology for ultra-tiny silicon-based inductor, which has the capability to regulate voltage and to filter out high frequency noise for power management integrated circuits (PMICs). As 5th Generation (5G) communication network and High Performance Computing (HPC) applications are expected to surge in the coming decade, computing power is projected to grow exponentially and power management is getting more critical than ever for mobile devices and HPC applications to save energy. As compared to traditional Surface Mount Device (SMD) inductors on package substrate, silicon-based inductor integrated in System on Chip (SoC) for better power management performance. And its form factor is also much smaller than discrete inductors. However, its inductance (less than 10 nanohenries) can only be measured by laboratory instruments which cannot meet mass production test throughput requirements for yield learning. In this paper, we propose an ATE-based test methodology that leads to highly accurate and reliable measurements for production test of silicon-based inductors.

Integrated passive devices (IPDs) have been widely used in advanced packaging of semiconductor chips, to improve their power integrity and impedance matching. There is a growing demand in guaranteeing signal and power integrity for the chips used in safety-critical products, such as those used in automotive, aviation, industrial, and defense systems, where IPDs help improve quality and reliability of the chips. Therefore, IPD testing and screening itself is essential. Note that the cost of replacing failed IPDs is much higher than the cost of manufacturing them, so screening bad IPDs before mounting is also crucial. In this work, we propose a machine learning (ML) based screening methodology to identifying the IPDs that have potential reliability issues. Based on the parametric data of 360,000 IPDs collected from the wafer probing test, the proposed Semiconductor Quality Net (SQnet) is trained to predict the IPDs which have low breakdown voltage, i.e., low reliability. Keeping the overkill rate below 10%, our method can screen out 6 to 15X more bad dies than the existing industrial methods, i.e., DPAT and GDBC.

This paper introduces a high quality screening methodology, using Integrated Passive Device (IPD) as an example device, which has the capability to increase power integrity of Integrated Fan Out Wafer Level Chip Scale Package (InFO WLCSP). InFO WLCSP is a more cost effective solution to achieve “More than Moore's law” for mobile devices than 3D integrated circuits (3DIC). Ultra-thin IPD with high capacitance density is capable to further shrinking InFO package dimensions and boosting its performance. Although the cost percentage of an IPD in the whole InFO package is negligible, a defective IPD can cause the whole InFO package malfunctioned. Traditional test methods such as good die in a bad cluster (GDBC) and dynamic part averaging testing (DPAT) are used screening IPD devices, however it is insufficient for high quality screen standards. In this paper, we propose a novel methodology that leads to an effective screening method to guarantee high quality and reliable IPD devices for InFO packages. We will show results on some industrial cases to validate our claims.

This paper introduces test solutions for Integrated Fan Out Wafer Level Chip Scale Packaging (InFO WLCSP) which has the promising of being a very cost effective solution to achieve “More than Moore's law” for mobile devices - more so than 3D integrated circuits (3DIC). InFO WLCSP has its own unique test challenges and it is important to have high-quality screen methodology for severe defects and potential reliablity failures. In this paper we propose novel solutions that leads to fast and reliable tests for InFO WLCSP packages. We will show results on some industrial cases to validate our claims.

The Integrated Fan Out (InFO) technology can accom-plish package miniaturization and successfully achieve “More than Moore's Law.” Its substrate-free technology also brings great cost-effective attraction to mobile and wearable applications. Ultra-thin integrated passive devices (IPDs) with high capacitance density can further shrink the InFO size and boost the bandwidth. Although the cost for the IPD in the InFO package is negligible, failed IPDs can shut down the whole InFO package. This would cause an entire mobile system loss about 104times of cost penalty. Thus the quality of each IPD chip must be ensured before surface-mounted on the InFO, and applying the final testing (FT) of the IPD is necessary. In this paper, we propose a novel optical positioning FT system combined with testing-for-manufacturing (TFM) methodology for the ultra-thin IPD chips testing. For validation of the novel comprehensive FT solution in the volume production domain, ultra-thin and ultra-small-area IPD chips with several millions sample sizes have passed through the FT system.

Redundancy repair is a commonly used technique for memory yield improvement. In order to ensure high repair rate and final product yield, it is necessary to develop a repair scheme for the coming three-dimensional (3D) architecture of stacked DRAM. According to the JEDEC mobile memory technology roadmap, the interface of 3D DRAM, including the Wide I/O and High-Bandwidth Memory (HBM), is mainly classified as channel-based memories. In this paper, we propose a built-off self-test(BOSR) scheme at the controller level for channel-based 3D memory to enhance final product yield after the bonding of a memory cube to its corresponding logic die. The logic die contains the Channel controller, in which the BOSR circuit resides. Experimental results show that the repair rate is high with higher cluster failure ratio due to the flexible algorithm we choose. The area overhead is low and it decreases significantly when the memory size or channel count increases. The performance penalty is also low due to the parallel execution of address comparison and repair. Moreover, the manufacture cost is lower than conventional DRAM architecture due to allocator-based redundancies. Finally, the proposed scheme can easily be applied to other channel-based 3D memories.

With the increasing demand of super high scale of integration and small form factor in advanced semiconductor products, especially those that integrate DRAM and logic dies, 3D IC and Wafer-Level Chip-Scale Packaging (WLCSP) are considered promising approaches. In Integrated Fan-Out (InFO) WLCSP, a large number of fine-pitch pads, where neighboring pads cannot be probed simultaneously due to insufficient pitch, are used as the contact interfaces of inter-die interconnections. If the fine-pitch pads cannot be probed, the interconnections between the pads and boundary scan cells (BSCs) cannot be tested, which can lead to higher defect level. From industrial investigation, untested fine-pitch pads lead to 1-2% test coverage loss. To improve the overall test coverage, in this paper, we propose a pre-bond probing methodology for fine-pitch pads of InFO WLCSP. By the proposed probing schemes, open/short faults on the interconnects between the fine-pitch pads and BSCs can be all tested by the ATE. Moreover, for short faults that only occur between adjacent pads (interconnects), we propose a grouping method to determine the test patterns at each probing stage, which can minimize the test time. We also show that our method can achieve 100% test coverage of open/short faults.

Due to more aggressive design rules adopted by memories than logic circuits, memories have been considered as the major technology driver of advanced logic circuits, so far as CMOS process technology is concerned. Memory failure pattern identification therefore is important, and is traditionally considered a key task that can help improve the efficiency of memory diagnosis and failure analysis. Critical failure patterns (that are the yield killers), however, may change in different memory designs and process technologies. It is difficult to identify critical failure patterns from high-volume memory failure bitmaps if they are not predefined. To solve this problem, we propose a local parallel search algorithm for efficient memory failure pattern identification. In addition, the proposed system integrates the defect-spectrum-based and coordinate-distance-based methods to identify critical memory failure patterns from a large amount of memory failure bitmaps automatically, even if they are not defined in advance. In our experiment for 132,488 4-MB memory failure bitmaps, the proposed system can automatically identify six critical yet undefined failure patterns in minutes, in addition to all known patterns. In comparison, the state-of-the-art commercial tools need manual inspection of the memory failure bitmaps to identify the same failure patterns.

This paper introduces a probing methodology for Integrated Fan Out Wafer Level Chip Scale Packaging (InFO WLCSP) which has the promise of being a very cost effective solution to achieve “More than Moore's law” for mobile devices - more so than 3D integrated circuits (3DIC). InFO WLCSP can use either Aluminum (Al) pads or Copper (Cu) pillars as contact interfaces. Cu pillars without solder caps are selected as the contact interface due to their superior area and cost efficiency. However, there are some challenges due to Cu oxidation and its small size. In this paper we propose a novel methodology that leads to a very high precision test resulting in better yield for mass production of InFO WLCSP packages. We will show results on some industrial designs to validate our claims.

The three-dimensional integrated circuit (3D IC) is considered a promising approach that can obtain high data band-width and low power consumption for future electronic systems that require high integration level. One of the popular drivers for 3D IC is the integration of a memory stack and a logic die. Because the yield of a 3D IC is the product of respective yields of the mounted dies, the yields of the memory dies and logic die must be high enough, or the 3D IC will be too expensive to be manufactured. To obtain a high yield of 3D ICs, efficient test and repair methodologies for memories are necessary. In this paper, we target the channel-based 3D dynamic random access memory (DRAM) and propose two 3D redundancy architectures, i.e., Cubical Redundancy Architectures 1 and 2 (CRA1 and CRA2). We use Wide-IO DRAM as an example for discussion. In CRA1, spares are associated with each DRAM die as in a conventional 2D architecture. In CRA2, we use a static random access memory (SRAM) on the logic die as spares. Experimental results show that the CRA1 can achieve up to 18% higher stack yield than traditional redundancy architecture with the same area overhead. On the other hand, the CRA2 can achieve the same yield as the CRA1 with 40% less spares, but 1.3% higher area overhead.

This paper describes an on-chip intellectual property (IP) testing platform, Universal High Frequency Test structure (UHFTs), which makes logic, memory, and analog / mixed-signal IPs at-speed testable in the same testing structure. Any functional testing pattern can be loaded from an external pattern generator or a tester through standard 5-pin JTAG interfaces operating at 10 MHz or below. The on-chip multichannel JTAG interface and elastic buffers convert an externally supplied pattern to an on-chip at-speed high-frequency pattern. The pattern can have address, data, and control fields. Each field is applied as input to a DUT in anyone of 16 available DUT sites, fully synchronized to the on-chip global clock. The output from the DUT is captured at-speed and stored in an output buffer. The content of the output buffer is read out to an external tester through the elastic-buffer and JTAG interfaces under a program control. UHFTs, implemented in TSMC 28-nm High Performance CMOS process, has been successfully used in digital, including ATPG, BIST, and vector-based tests with the capability of mixed-signal and analog tests. UHFTs have been designed with a frequency goal of 4 GHz in TSMC 28-nm CMOS process in the slow corner.

Recent advances in semiconductor process technology especially interconnects using Through Silicon Vias (TSVs) enable the heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and stacked in a 3D form. TSMC has developed the CoWoS™ (Chip on Wafer on Substrate) process as a design paradigm to assemble silicon interposer-based 3D ICs. To reach quality requirements for volume production, several test challenges related to 3D ICs need to be addressed. This paper describes the test and debug strategy used in designing a CoWoS™ based stacked IC. The 3D design presented in the paper contains three heterogeneous dies (a logic, a DRAM, and a JEDEC Wide-I/O compliant DRAM) stacked on the top of a passive interposer. For passive interposer testing, a novel test methodology called Pretty-Good-Die (PGD) test is presented, while for inter-die test, a novel scalable multi-tower 3D DFT architecture is presented. Silicon results show that most of the test challenges can be solved efficiently if planned properly; and 3D ICs are reality and not a fiction anymore.

High-density probing is a main trend of the test technology. The warping issues of probe card are caused by the high-density test. The metal backer and patches are applied to solve this problem and the optimized sizes of backer and patches are decided by the proposed flow. Using the probe card with optimized backer and patches, the stability of test can be ensured and the test yields are increased. 26.56% test-yield improvement can be obtained.

Through-Silicon-Via (TSV)-based three-dimensional ICs (3D-ICs) have gained increasing attention due to their potential in reducing manufacturing costs and capability of integrating more functionality into a single chip. One of the most important factors that affect 3D-IC yield is the integrity of interconnects which connect different dies in a 3D-IC. This paper proposes a Design-for-Test (DIT) scheme that can 1) detect faulty interconnects in 3D-ICs, 2) pinpoint open defect locations to help yield learning, and 3) repair faulty interconnects caused by open defects to improve the 3D-IC yield. Experimental results show that the proposed scheme can achieve a diagnosis resolution of 84% for open defects. With the interconnect repair mechanism, the 3D-IC yield is improved by 10%. In addition, cost-benefit analysis reveals that the proposed technique can significantly increase the net profit, especially when the natural interconnect yield is low.

Error correction code (ECC) and built-in self-repair (BISR) schemes have been wildly used for improving the yield and reliability of memories. Many built-in redundancy-analysis (BIRA) algorithms and ECC schemes have been reported before. However, most of them focus on either BIRA algorithms or ECC schemes. In this paper, we propose an ECC-Enhanced Memory Repair (EEMR) scheme for yield improvement. Many modern memories are equipped with ECC in addition to BISR. We evaluate the back-end flow that combines both ECC and BIRA to determine whether yield can be improved by proper sequencing of the two steps. We also collect and identify important failure patterns and their distributions from over 100,000 sample memory instances, which are used to enhance the EEMR scheme that incorporates ECC. As ECC is failure pattern sensitive, careful evaluation from realistic failure bitmaps is necessary. We also verify the feasibility of implementing the proposed EEMR scheme by real test data. Experimental results from industrial 4Mb memory instances show that the proposed EEMR scheme gains over 2% instance yield on average, as compared with the traditional scheme. We also investigate the reliability of the EEMR scheme with different ECC specifications and BIRA algorithms.