Bin You

dblp:124/3575 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2026
0000-0001-7549-8665ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 67% Integrated circuit design · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits
1.012026
An Unsupervised Learning-Based Multidimensional Scaling Approach for Placement and Routing of Monolithic Microwave Integrated Circuit · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Electronic design automation
physical design
1.012026
An Unsupervised Learning-Based Multidimensional Scaling Approach for Placement and Routing of Monolithic Microwave Integrated Circuit · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Electronic design automation › physical design
placement and routing
1.012026
An Unsupervised Learning-Based Multidimensional Scaling Approach for Placement and Routing of Monolithic Microwave Integrated Circuit · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026

Methods — techniques the papers use, named apart from their topics

multidimensional scaling · 1.0dimensionality reduction · 1.0analytical optimization · 1.0
YearPublicationVenuePosition
2026 An Unsupervised Learning-Based Multidimensional Scaling Approach for Placement and Routing of Monolithic Microwave Integrated Circuit
abstract
The layout method for Radio Frequency/Monolithic Microwave Integrated Circuit (RF/MMIC) is one of the key components in achieving MMIC design automation. Our work proposes a multi-stage progressive automated layout framework addressing MMIC layout challenges under 0.25 μmGaAs pHEMT technology. This framework employs dimensionality reduction from unsupervised learning, integrates practical layout design rules, and achieves automated layout through analytical optimization methods. Applied to multiple cases including filters, low-noise amplifiers (LNAs), and power amplifiers (PAs), the method successfully generated manufacturable layouts; the process achieves end-to-end automation from placement to routing, producing layouts that are verified to be DRC-clean. Simulation-verified results demonstrate comparable performance to manual designs while achieving ≥10× speedup over conventional methods. We believe this work contributes valuable attempts toward automated MMIC layout generation and advances progress in MMIC design automation.
Yaqi Wang 0002, Bin You, Jun Liu 0027
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.5