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H. S. Miller

dblp:124/5934 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1964
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 43% Emerging computing paradigms · 28% Memory systems · 28%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms › neuromorphic computing
associative memory
0.011964
Resolving Multiple Responses in an Associative Memory · IEEE Trans. Electron. Comput. 1964
Memory systems › content-addressable memory
multiple response resolution
0.011964
Resolving Multiple Responses in an Associative Memory · IEEE Trans. Electron. Comput. 1964
Electronic design automation
logic synthesis
0.011962
Majority-Logic Synthesis by Geometric Methods · IRE Trans. Electron. Comput. 1962
Electronic design automation › logic synthesis › threshold logic synthesis
majority-logic synthesis
0.011962
Majority-Logic Synthesis by Geometric Methods · IRE Trans. Electron. Comput. 1962

Methods — techniques the papers use, named apart from their topics

geometric methods · 0.0bit plane sensing · 0.0
YearPublicationVenuePosition
1964 Resolving Multiple Responses in an Associative Memory
abstract
An interrogation routine is described which retrieves k multiple responses in, at best, (k+1) memory cycles and, at worst, (2k-1) memory cycles. In comparison, the fastest routine described in the literature, Lewin's routine5, always requires (2k-1) memory cycles. The reduction in number of memory cycles achieved by this interrogation routine is at the expense of some sophistication in the bit plane sensing device, namely, distinguishing between no signal, one unit of signal, and more than one unit of signal rather than distinguishing between absence and presence of signal. For large word lengths in respect to the average number of multiple responses, it is apparent that the best case will be expected.
H. S. Miller
IEEE Trans. Electron. Comput.1
1962 Majority-Logic Synthesis by Geometric Methods
H. S. Miller, Richard O. Winder
IRE Trans. Electron. Comput.1